TMS320F28377S: Opens/Shorts Detection Circuit (ADC module)

Hi Geon Kim,

We do not have an application note for this feature yet but it is something that we can add in the future. The open-short detection block is a way to do a self-test of the physical channel connections on the ADC to ensure that the channels in use are not shorted (to ground or to other sources) or left as an open circuits.

Users might have a need to check the integrity of connections to the ADC channel especially when making critical measurements as a first step. This is where this feature will be useful.

As shown in the circuit diagram, there is a voltage divider resistor network after the channel multiplexer. The resistor network can be switched to be sourced from VDDA or VSSA or a combination of these. There are four internal switches that make the connection to VDDA or VSSA. This is controlled by register ADCOSDETECT and has 8 possible switch combinations. See table 9-9 for the complete truth table. Column 1 of that table shows the possible DETECTCFG values, columns 3-6 show the state of the 4 switches (they are either open, connected to VDDA or connected to VSSA). Source voltage and channel impedances for each of the corresponding DETECTCFT values are shown in columns 2 and 7 respectively.

One important thing to note here is that the source voltage and impedances stated in table 9-9 will be affected by how the channel is connected externally. For example, assume that in the ADC channel setup, channel A4 is selected (AdcaRegs.ADCSOCCTL.bit.CHSEL = 4) and DETECTCFG is set to 2 (AdcaRegs.ADCDETECTCFG.DETECTCFG = 2). Also assume that externally, channel A4 has a series resistor of 100 ohms that is connected to a signal source, but self testing purposes, the signal source feeding channel A4 is intentionally opened (high impedance). In this setup scenario, channel A4 is biased internally by VDDA (per truth table in 9-9). Conversion result will then be at full scale. If DETECTCFG value is changed to 0, then A4 is biased by VSSA so conversion result is close to zero scale. If the signal source in A4 is closed, whatever the signal voltage present will provide additional bias to the OS detect network through the assumed external series resistance of 100 ohms. You would then have to do a source/resistance node calculation to check the effective source voltage seen by the ADC. Users can choose different values of DETECTCFG, factoring in the current values of external voltage sources and impedances and generate a self-test on the channel connections. This is just a simple illustration on how this OS block feature is used.

Hopefully, this will give you an idea on how to use this feature in your applicatication.

Best regards,
Joseph