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TMS320F28069: Complementary PWM signals

farid mabr
Intellectual 810 points
Part Number: TMS320F28069

  Hi,

I defined PWM1A as a master:

   EALLOW;
   /* Assumes ePWM1 clock is already enabled in InitSysCtrl(); */
   EPwm1Regs.ETSEL.bit.SOCBEN = 1;        /* Enable SOC on B group */
   EPwm1Regs.ETSEL.bit.SOCBSEL = 6;       /* Select SOC from from CPMB on upcount */
   EPwm1Regs.ETPS.bit.SOCBPRD = 1;        /* Generate pulse on 1st event */

   /* Set period / duty / count mode */
   EPwm1Regs.TBPHS.half.TBPHS = 0;             /* Set Phase register to zero */
   EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;     /* Phase loading disabled */
   EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;    /* Clock ratio to SYSCLKOUT */
   EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
   EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;

   EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;          /* Set PWM1A on Zero */
   EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;        /* Clear PWM1A on match on count A up */
   EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET;          /* Set PWM1B on Zero */
   EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR;        /* Clear PWM1B on match on count B up */

   EPwm1Regs.CMPB = DutyCycle_PWMB;                       /* Set compare B value */
   EPwm1Regs.CMPA.half.CMPA = DutyCycle_PWMA;             /* Set compare A value */
   EPwm1Regs.TBPRD = PERIOD;                   /* Set period for ePWM1 */
   EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;  /* Count up and start */
   EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;
   EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // sync "down-stream"
   EDIS;

and I want to generate a PWM compementary signals on PWM3:

  /* Assumes ePWM3 clock is already enabled in InitSysCtrl(); */
   EALLOW;
   /*PWM3: Set period / duty / count mode */
   EPwm3Regs.TBPHS.half.TBPHS = 0;             /* Set Phase register to zero */
   EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;      /* Phase loading disabled */
   EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;    /* Clock ratio to SYSCLKOUT */
   EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
   EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;

   EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET;          /* Set PWM3A on Zero */
   EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR;        /* Clear PWM3A on match on count A up */
   EPwm3Regs.AQCTLB.bit.ZRO = AQ_SET;          /* Set PWM3B on Zero */
   EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR;        /* Clear PWM3B on match on count B up */

   //EPwm3Regs.CMPB = DutyCycle_PWMB;                       /* Set compare B value */
   EPwm3Regs.CMPA.half.CMPA =DutyCycle_PWMA;             /* Set compare A value */
   EPwm3Regs.TBPRD = PERIOD;                             /* Set period for ePWM3 */
   EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;            /* Count up and start */
   EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;
   EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;           // sync "down-stream" slave
   EDIS;


   /* Configure trip zone based on Comparator 3 output and configure blanking */
   EALLOW;
   EPwm3Regs.TZSEL.bit.DCAEVT2 = 0;                      /* Digital compare, output A, cycle by cycle */
   EPwm3Regs.TZCTL.bit.TZA = TZ_FORCE_LO;                /* EPWM3A will go low */
   EPwm3Regs.TZCTL.bit.TZB = TZ_FORCE_HI;                /* EPWM3B goes HI */

   EPwm3Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_COMP1OUT;    // DCAH = Comparator 1 output
   EPwm3Regs.TZDCSEL.bit.DCAEVT2 = TZ_DCAH_HI;           /* DCAEVT2 =  DCAL High (will become active as Comparator output goes High) */
                                                         /* DCAEVT2 = DCAH high (will become EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_COMP2OUT; DCAH = Comparator 2 output*/
   EPwm3Regs.DCACTL.bit.EVT2SRCSEL = DC_EVT2;            /* DCAEVT2 = DCAEVT2 (not filtered) */
   EPwm3Regs.DCACTL.bit.EVT2FRCSYNCSEL = DC_EVT_ASYNC;   /* Take async path */
   EPwm3Regs.DCFCTL.bit.PULSESEL = 0;                    /* Time-base counter equal to period (TBCTR =TBPRD) */
   EPwm3Regs.DCFCTL.bit.BLANKINV = 0;                    /* Blanking window inverted */
   EPwm3Regs.DCFCTL.bit.BLANKE = 1;                      /* Blanking Window Enable */
   EPwm3Regs.DCFCTL.bit.SRCSEL = 0;                      /* Source Is DCAEVT1 Signal */
   EPwm3Regs.DCFWINDOW = 0; //34;                        /* length blanking window: this corresponds to: 34*11.1ns=377.4ns*/
   EPwm3Regs.DCFOFFSET = 5;                              /* 5*11.1=55.5ns blanking window offset & then blanking window begins */
   EDIS;

   // Active high complementary PWMs - Set up the deadband
   EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;
   EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
   EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
   EPwm3Regs.DBRED = 0;//15;
   EPwm3Regs.DBFED = 0;//15;

However, after I run my code I could only see channel 3B on the scope but not channel B. I made sure PWM3 GPIOs are configured properly.

Can anyone, tell me why is that happening?

  • 0
    TI__Guru 52040 points
    Can you clarify "I could only see channel 3B on the scope but not channel B"?
  • 0 in reply to Nima Eskandari
    Intellectual 810 points
    I only see PWM3B signal, not PWM3A
  • 0 in reply to farid mabr
    Intellectual 810 points

    I am trying to control PWM3,4,5 with comparators 1, 2, and 3 respectively. However, I am seeing only PWM4 is behaving as it should. PWM3A and PWM5A stays low as soon as they trip for the first time, because of comparator 1, and 3 goes high. I noticed that when there is a trip TZFLG register get set, and it never gets cleared in the next cycle( when comparator output becomes low).

    Please my attached hardware config file:

    HwConfig.zip

  • 0 in reply to farid mabr
    TI__Guru 52040 points

    Are you using OST mode? You need to make sure your ePWM Trip zone is configured in Cycle by cycle mode. Aslo make sure to clear the flags for the corresponding EPWM Cycle by Cycle interrupt.

    //
// epwm2TZISR - ePWM2 TZ ISR
//
__interrupt void epwm2TZISR(void)
{
    epwm2TZIntCount++;

    //
    // Toggle GPIO to notify when TZ is entered
    //
    GPIO_togglePin(11);

    //
    // Clear the flags - we will continue to take this interrupt until the TZ
    // pin goes high.
    //
    EPWM_clearTripZoneFlag(EPWM2_BASE, (EPWM_TZ_INTERRUPT | EPWM_TZ_FLAG_CBC));

    //
    // Acknowledge this interrupt to receive more interrupts from group 2
    //
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP2);
}