TMS320F28379D: PWM Default System Clock

Hi Manohar,

Please check the description of the above mentioned register bits as this config would lead to 25 MHz. E.g.
ClkCfgRegs.PERCLKDIVSEL[EPWMCLKDIV] = 2; // this configures epwmclk = 200MHz as x0 = /1 of PLLSYSCLK

TBCTL[HSPCLKDIV] = 1; // configures /2
TBCTL[CLKDIV] = 2; // configures /4
Above config results in TBCLK = 200Mhz/(2x4) = 25Mhz

Thanks
Vasudha

Hi Vasudha,

Appreciate your fast reply.

I have checked the registers you shared with me and below are the register values(default)
ClkCfgRegs.PERCLKDIVSEL[EPWMCLKDIV] = 1; // configures/2
TBCTL[HSPCLKDIV] = 0; // configures/1
TBCTL[CLKDIV] = 1; // configures/2
Configured PLLSystemClock to be 200Mhz. From the above register settings I should get TBCLK to be 50Mhz,But its giving me 25Mhz.

Tpwm = (TBPRD + 1) * Ttbclk; //TBPRD = 0
My PWM is UP counter mode, I have made the TBPRD register to zero. So the Tpwm = Ttbclk.

Question:
Instead of 50Mhz, Why I am getting 25Mhz? Is there any configuration I am still missing?

Regards,
Manohar

Hi Manohar,

You should not be setting TBPRD value to zero. Please refer to EPWM examples in C2000Ware to get more details on pwm configuration.

Thanks
Vasudha

Thank you Vasudha.
I know that TBPRD register is to get the exact clock frequency of PWM.

Tpwm = (TBPRD + 1) * Ttbclk; //TBPRD = 0

The above formula is for PWM frequency calculation. I want to map the TBCLK directly to PWM clock, So making it as zero.

Just confirm me what exact TBCLK I will be getting if I configure the following register with 200Mhz System Clock?
ClkCfgRegs.PERCLKDIVSEL[EPWMCLKDIV] = 1; // configures/2
TBCTL[HSPCLKDIV] = 0; // configures/1
TBCTL[CLKDIV] = 1; // configures/2

I am getting 25Mhz clock in PWM pin.


Regards,
Manohar

Just confirm me what exact TBCLK I will be getting if I configure the following register with 200Mhz System Clock?
ClkCfgRegs.PERCLKDIVSEL[EPWMCLKDIV] = 1; // configures/2
TBCTL[HSPCLKDIV] = 0; // configures/1
TBCTL[CLKDIV] = 1; // configures/2

The above configuration will set TBCLK as 50 MHz. But I think you have configured the time-base counter in up-down mode and since the TBPRD value is 0, the output frequency is coming as 25 MHz.

To get 50 MHz frequency, you can configure TBCLK as 100 MHz and TBPRD value as 1.

Thanks

Vasudha

Hi Vasudha,

Just clarify me only one thing. So that I don't want you to get distracted from my query.

System Clock = 200Mhz //From PLL
Time Base counter mode = UP_MODE
ClkCfgRegs.PERCLKDIVSEL[EPWMCLKDIV] = 1; // configures/2
 TBCTL[HSPCLKDIV] = 0; // configures/1
 TBCTL[CLKDIV] = 1; // configures/2
TBPRD = 1;

With the above configuration, what is the expected PWM frequency?

Regards,
Manohar

yes correct.