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TMS320F280049: documentation for pullup/pulldown for analog inputs (port H)

Lenio Cacula
Genius 17010 points

Part Number: TMS320F280049
Other Parts Discussed in Thread: C2000WARE

The TRM describes the disabling of the pullups for GPIOA/B, but does not mention whether pullups are also present in the analog port GPIOH. I understand the open circuit detect that is implemented after the ADC multiplexer, but the question is before the multiplexer. Table 4.9 of the datasheet mentions that analog inputs DO feature pullup resistors, but where is the correspondent GPHPUD register? Any comments that help me understand this issue are welcome!

Thank you!

  • 0
    TI__Guru 55700 points
    Lenio,

    We are looking into this issue. Please expect a reply from us in next 2 -3 business days.

    Regards,
    Manoj
  • 0 in reply to Manoj Santha Mohan
    TI__Guru 55700 points
    Lenio,

    We are still working on this item. Please expect a reply before end of this week.

    Regards,
    Manoj
  • 0 in reply to Manoj Santha Mohan
    TI__Guru 60865 points
    Hi Lenio,

    These do indeed exist. It looks like we missed documenting the registers, so they are hidden in both the SW and the TRM.

    We'll start the process of having these added. It will probably take awhile to show up in the TRM since an update to this document was recently published. I'll have to check on the C2000ware release schedule to determine how long it will take for these to show up in C2000ware.
  • 0 in reply to Devin Cottier
    TI__Genius 17010 points
    Hi Devin,

    is it possible to share the address of those missing registers?

    Thank you!
  • 0 in reply to Lenio Cacula
    TI__Guru 60865 points
    Hi Lenio.

    The 16-bit memory location offset for GPH PUD is 0x1CC.

    For reference, GPHQSEL2 (the previous register in the module) is at 0x1C4.

    Bit 0 is PUD for GPIO224 and each subsequent bit is for the next GPIO (e.g. Bit 1 is for GPIO225)

    At reset all fields are '1' = pull-up disabled.

    This is a 32-bit register.
  • 0 in reply to Devin Cottier
    TI__Genius 17010 points

    Can you please confirm if this table generated by the customer is correct? This is the mapping for GPHPUD.

    GPHPUD Register            

    31

    30

    29

    28

    27

    26

    25

    24

    AIO255

    AIO254

    AIO253

    AIO252

    AIO251

    AIO250

    AIO249

    AI0248

    reserved

    reserved

    reserved

    reserved

    reserved

    reserved

    reserved

    reserved

     

     

     

     

     

     

     

     

    23

    22

    21

    10

    19

    18

    17

    16

    AI0247

    AIO246

    AIO245

    AIO244

    AIO243

    AIO242

    AIO241

    AIO240

    reserved

    C14

    C3

    C2

    B5

    B3

    B0

    C5

     

     

     

     

     

     

     

     

    15

    14

    13

    12

    11

    10

    9

    8

    AIO239

    AIO238

    AIO237

    AIO236

    AIO235

    AIO234

    AIO233

    AIO232

    C4

    C1

    C0

    A9

    reserved

    A5

    A3

    A1

     

     

     

     

     

     

     

     

    7

    6

    5

    4

    3

    2

    1

    0

    AIO231

    AIO230

    AIO229

    AIO228

    AIO227

    AIO226

    AIO225

    AIO224

    A0/B15/C15

    A10/B1/C10

    A8

    A6

    B4/C8

    B2/C6

    A4/B8

    A2/B6

     

     

     

     

     

     

     

     

     

    GPHPUD Register Field Descriptions

    Bit

    Field

    Type

    Reset

    Description

    31

    AIO255

     

    1h

    Reserved

    30

    AIO254

     

    1h

    Reserved

    29

    AIO253

     

    1h

    Reserved

    28

    AIO252

     

    1h

    Reserved

    27

    AIO251

     

    1h

    Reserved

    26

    AIO250

     

    1h

    Reserved

    25

    AIO249

     

    1h

    Reserved

    24

    AIO248

     

    1h

    Reserved

    23

    AIO247

     

    1h

    Reserved

    22

    AIO246 : C14

    R/W

    1h

    Pull-up disable for C14

    21

    AIO245 : C3

    R/W

    1h

    Pull-up disable for C3

    20

    AIO244 : C2

    R/W

    1h

    Pull-up disable for C2

    19

    AIO243 : B5

    R/W

    1h

    Pull-up disable for B5

    18

    AIO242 : B3

    R/W

    1h

    Pull-up disable for B3

    17

    AIO241 : B0

    R/W

    1h

    Pull-up disable for B0

    16

    AIO240 : C5

    R/W

    1h

    Pull-up disable for C5

    15

    AIO239 : C4

    R/W

    1h

    Pull-up disable for C4

    14

    AIO238 : C1

    R/W

    1h

    Pull-up disable for C1

    13

    AIO237 : C0

    R/W

    1h

    Pull-up disable for C0

    12

    AIO236 : A9

    R/W

    1h

    Pull-up disable for A9

    11

    AIO235 :

     

    1h

    Reserved

    10

    AIO234 : A5

    R/W

    1h

    Pull-up disable for A5

    9

    AIO233 : A3

    R/W

    1h

    Pull-up disable for A3

    8

    AIO232 : A1

    R/W

    1h

    Pull-up disable for A1

    7

    AIO231 : A0/B15/C15

    R/W

    1h

    Pull-up disable for A0/B15/C15

    6

    AIO230 : A10/B1/C10

    R/W

    1h

    Pull-up disable for A10/B1/C10

    5

    AIO229 : A8

    R/W

    1h

    Pull-up disable for A8

    4

    AIO228 : A6

    R/W

    1h

    Pull-up disable for A6

    3

    AIO227 : B4/C8

    R/W

    1h

    Pull-up disable for B4/C8

    2

    AIO226 : B2/C6

    R/W

    1h

    Pull-up disable for B2/C6

    1

    AIO225 : A4/B8

    R/W

    1h

    Pull-up disable for A4/B8

    0

    AIO224 : A2/B6

    R/W

    1h

    Pull-up disable for A2/B6

    Thank you!

  • 0 in reply to Lenio Cacula
    TI__Guru 60865 points
    Hi Lenio,

    Yeah, those tables are correct.
  • 0 in reply to Devin Cottier
    Guru 14640 points
    Except for 2 bit "10's"...