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TMS320F28379D: Incoherence for ADC Timings in 12-Bit Mode

Part Number: TMS320F28379D

Hello everyone,

I am working on a system in which I need to assure the realtime management to be able to read the ADC result in the right moment. I found an incoherence in ADC Timings in 12-Bit Mode table for tLAT, tINT(Early) and tINT(LATE), between the datasheet (SPRS880J revised may 2018, Table 5-51 on page 110) and the technical reference manual (SPRUHM8G revised september 2017, table 10-10 on page 1412). Could you please confirm me that which table I can use for the realtime management? And how can I verify that?

Thanks a lot for any answer!

Lam

  • Hi LE,

    Currently looking at the documents. Will get back with you for answers...

    Best regards,
    Joseph
  • Hi LE,

    There is already a request to update the ADC timings on the Technical Reference Manual (SPRUHM8G). The correct ADC timings are reflected in the Datasheet.

    Verifying this is not straightforward, but you can try the procedure below:

    - Configure SOC0 to be SW triggered.
    - Let end of SOC0 set ADCINT1 flag (ADCINTSEL1N2.INT1SEL = 0).
    - Map and define an ISR for ADCINT1. In that ISR, initiate ePWM to start counting. Make sure to clock ePWM with SYSCLK (no prescale).
    - Configure SOC1 to be triggered by ADCINT2 (ADCINTSOCSEL1.SOC1 = 2). Map and define an ISR for ADCINT2. In this ISR, you can capture elapsed ePWM count.
    - Subtract S+H (or ACQPS + 1) setting from the elapsed ePWM count captured in ISR. This should give the number of SYSCLK cycles taken to convert SOC1.

    Best regards,
    Joseph
  • Hi Joseph,

    Thanks for your answer, I will try the procedure tomorow and keep your informed of the result.

    Best regards,
    Lam
  • Hi Lam,

    Have not heard from you in a while and I am assuming that you have the ADC timing issue resolved, hence marking this thread as "resolved". If this is still an issue for you, please don't hesitate to post in this forum so we can get it addressed.

    Best regards,
    Joseph