Other Parts Discussed in Thread: TIDM-1008, BOOSTXL-POSMGR, LAUNCHXL-F28379D, CONTROLSUITE,
Tool/software: Code Composer Studio
Hello everyone.
I recently did EnDat related works using a LaunchPad and a TIDM-1008 board.
Using these HWs, the EnDat related work was done successfully using an HIDENHAIN absolute encoder.
At TIDM-1008 document,Table 2. TIDM-1008 Board and BOOSTXL-POSMGR Connectors show the following things.
RELEVANT TI DESIGNS AND |
DESCRIPTION |
RELEVANT TI DESIGNS AND |
Abs-Enc-1 (J7) |
EnDat 2.1, EnDat 2.2, other absolute encoders |
TIDM-1008, BOOSTXL-POSMGR |
Abs-Enc-2 (J8) |
EnDat 2.1, EnDat 2.2, other absolute encoders |
Future TID + BOOSTXL-POSMGR |
Even though TIDM-1008 board has 2ea absolute encoder connector to support EnDat interface, only J7 connector is available in this time.
However, I need dual Endat interface to do specific purpose.
To do this work, I thought that if 2ea TIDM-1008 boards are used, 2ea EnDat interface is possible since LAUNCHXL-F28379D hardware has mirror image connectors as follows. .
LAUNCHXL-F28379D Connector |
Comments |
Site 1 (J1 J3 + J4 J2) |
x1 EnDat 2.1/2.2 or other Absolute Encoder and PTO |
Site 2 (J5 J7 + J8 J6) |
x1 EnDat 2.1/2.2 or other Absolute Encoder and PTO |
To verify my idea, I attached a TIDM-1008 board to Site 1, and modified source code as follows.
(See F28379D LaunchPad Pin Out and Pin Mux Options at ”sprui77b Page 8~9” )
|
Site 1 (J1 J3 + J4 J2) |
Site 2 (J5 J7 + J8 J6) (Original Code) |
Comments |
CLB Related |
GPIO0 GPIO1 GPIO3 |
GPIO6 GPIO7 GPIO9 |
ENC-1-CLK SPI-1-CLK ENDAT_DIR |
SPI Related Blocks |
GPIO60 GPIO58 GPIO59 GPIO61 GPIO19 |
GPIO65 GPIO63 GPIO64 GPIO66 GPIO139 |
SPICCLK SPISMO SPISOMI SPISTE PWREN |
But its results is NG. (at endat.c)
//Ensure that EncData is now low
if (GpioDataRegs.GPBDAT.bit.GPIO58 == 1) { //63(original) => 58(modified)
ESTOP0;
}
Question
1) Is there any solutions or tips to solve this issue?
2) Why EPWM1~4 is defined at EnDat_Init( ) at endat.c for the following F28379D LaunchPad Pin Out and Pin Mux Options as follows.
Site 2 (J5 J7 + J8 J6) Case: Original Source
If the below table mapping is correct, EPWM7~8 should be defined.
But this odd mapping case, EnDat interface is OK.
CpuSysRegs.PCLKCR2.bit.EPWM1 = 1;
CpuSysRegs.PCLKCR2.bit.EPWM2 = 1;
CpuSysRegs.PCLKCR2.bit.EPWM3 = 1;
CpuSysRegs.PCLKCR2.bit.EPWM4 = 1;
EDIS;