Part Number: TMS320F28379D
Hi,
I am involved in the choice of a processor, for applications with certification constraints, and I could not find for this microprocessor, the granularity of the management of the access mechanism to the GSRAM. Is the priority is managed globally for the entire GSRAM ? (consequence if the DMA of CPU 1 uses the GSRAM, CPU2 waits) or is there a management on smaller blocks. Unfortunately, I did not find a clear answer for this microprocessor....
Best regards
C. VALPARD
