• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 2 answers
  • Subscribers 82 subscribers
  • Views 1265 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28379D: QEP capture period register value

Amrutha Haridas
Intellectual 270 points

Part Number: TMS320F28379D

Hi

The incremental encoder I am using has 2500 ppr and has EQEPA, EQEPB, EQEPI signals. I have selected quadrature count mode for position count mode. The QPOSCNT register value is incremented by 10000 counts for a complete rotation.

For speed estimation at low-speed operation, QEP capture period register value is used. If the prescale values for this timer is chosen as 1, the QCTMR is incremented at SYSCLK and QCPRD register holds the period count value between the last successive eQEP position events (what is given in manual).

Question: Can we say that when EQep1Regs.QEPSTS.bit.UPEVNT = 1, and the value of QPOSLAT is 2000, the QCPRD will have the period count value between 1999 and 2000?

  • 0
    TI__Mastermind 24095 points
    Hi,

    You can refer to Figure 17-15. eQEP Edge Capture Unit.
    Value captured would also be dependent on the QCLK divider you've used in your application (UPPS).
    The eQEP capture timer (QCTMR) runs from prescaled SYSCLKOUT and the prescaler is programmed
    by the QCAPCTL[CCPS] bits. The capture timer (QCTMR) value is latched into the capture period register
    (QCPRD) on every unit position event and then the capture timer is reset, a flag is set in
    QEPSTS:UPEVNT to indicate that new value is latched into the QCPRD register. Software can check this
    status flag before reading the period register for low speed measurement and clear the flag by writing 1.
  • 0 in reply to Subrahmanya
    Intellectual 270 points

    Hi

    The divider for QCLK is 1 and divider for SYSCLK is 32. values are read when QEPSTS[UPEVNT] =1 as shown below.

    The values of QCPRDLAT and QPOSLAT are saved into test variables and the flag is reset. These variables were stored in an array at an interval of 4ms. The motor was running at 20 rpm. The values of QPOSCNT was also logged. It is seen that the values of QPOSLAT are repeating for different readings, while QPOSCNT is incrementing as shown below.

    Why is this happening? Is it because of any flag reset issue?

    Also, coming back to my earlier question. Eg: The values in the second row. Does the QCPRDLAT value of 1852 represent the time period between Unit timer event 20648 and 20647?

    Thank you

    regards

    Amrutha

  • 0 in reply to Amrutha Haridas
    TI__Mastermind 24095 points

    Hi,

    My not completely clear on how/when you are reading QPOSLAT and QPOSCNT values in software.
    One possibility of expecting different values in QPOSCNT could be completely due to the time at which a read from CPU is being performed to this register. QPOSCNT is continuously changing with the incoming QEPA/B signals whereas QPOSLAT on the other hand is a latched value w.r.t. a certain event.

    Is your speed estimation matching your expected value? What exactly is the issue in the application?

    If the QEPCTL[QCLM] bit is set, then the position counter, capture timer, and capture period values are latched into the QPOSLAT, QCTMRLAT and QCPRDLAT registers, respectively, on unit time out. So, in your case it should represent the time lapsed between the last unit timer events.