Part Number: TMS320F28374S
Other Parts Discussed in Thread: CONTROLSUITE
Hi,
I upgraded my project to use CLA. I got my code working in RAM and then I had strange problems running it form FLASH. I did a similar upgrade on another project and had no suck problems.
The list of my strange problems is/was:
No boot at all,
SDFM compare filters interrupts triggering on their own,
external interrupts triggering on their own,
state machine reseting when an certain message would come on CAN (program state machine going where it should not)
...
My current problem is that my program gets stuck in a NMI_ISR (Default ISR -> Non-Maskable Interrupt) & the whole state machine reseting thing.
I tried to mess with the initialization of cla, interrupts ect. , with FLASH linkers, with compiler settings, ... I don't know where else to look.
My code that copies ramfunctions to ram and program to cla is:
memcpy((uint32_t *)&RamfuncsRunStart, (uint32_t *)&RamfuncsLoadStart, (uint32_t)&RamfuncsLoadSize );
....
memcpy((uint32_t *)&Cla1ProgRunStart, (uint32_t *)&Cla1ProgLoadStart,
(uint32_t)&Cla1ProgLoadSize );
memcpy((uint32_t *)&Cla1ConstRunStart, (uint32_t *)&Cla1ConstLoadStart,
(uint32_t)&Cla1ConstLoadSize );
See linkers and whole CLA initialization attached below.
Attachments:
//#############################################################################
//
// FILE: F2837x_FLASH_lnk.cmd
//
// TITLE: Linker Command File for the 2837x platform
//
// This file includes all RAM and FLASH blocks present on the
// 2837x and depending on the active build configuration(RAM or FLASH)
// the appropriate sections will either be loaded into RAM or FLASH
// blocks
//
// (C)Copyright $YEAR$, Texas Instruments, Inc.
//
//#############################################################################
// $TI Release: PACKAGE NAME $
// $Release Date: PACKAGE RELEASE DATE $
//#############################################################################
// NOTES:
// 1. In addition to this memory linker command file, add the header linker
// command file directly to the project. The header linker command file is
// required to link the peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in
// controlSUITE\device_support\f2837x\F2837x_headers\cmd
//
// For BIOS applications add: F2837x_Headers_BIOS_cpuX.cmd
// For nonBIOS applications add: F2837x_Headers_nonBIOS_cpuX.cmd
//
// 2. On reset all RAMGSx blocks are under the mastership of CPU1. The user
// must configure the appropriate control registers to transfer mastership
// of a RAMGSx block over to CPU2
//
// 3. Memory blocks on F2837x are uniform (ie same physical memory) in both
// PAGE 0 and PAGE 1. That is the same memory region should not be defined
// for both PAGE 0 and PAGE 1. Doing so will result in corruption of program
// and/or data.
//
// Contiguous SARAM memory blocks can be combined if required to create a
// larger memory block.
//
//#############################################################################
// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
//
// NOTE: CLAScratch is no longer in use and is superceded by
// .scratchpad. It is kept here for legacy libraries
//
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
MEMORY
{
PAGE 0 :
BEGIN : origin = 0x080000, length = 0x000002
RAMMall : origin = 0x000002, length = 0x00800
RAMD0 : origin = 0x00B000, length = 0x000800
RAMD1 : origin = 0x00B800, length = 0x000800
RAMLS0in1 : origin = 0x008000, length = 0x001000
RAMGS8 : origin = 0x014000, length = 0x001000
RAMGS9 : origin = 0x015000, length = 0x001000
RAMGS10 : origin = 0x016000, length = 0x001000
RAMGS11 : origin = 0x017000, length = 0x001000
RESET : origin = 0x3FFFC0, length = 0x000002
/* Flash sectors */
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
PAGE 1 :
BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
RAMLS2in3 : origin = 0x009000, length = 0x001000
RAMLS4in5 : origin = 0x00A000, length = 0x001000
RAMGS3in4 : origin = 0x00F000, length = 0x002000
RAMGS5in6 : origin = 0x011000, length = 0x002000
RAMGS7 : origin = 0x013000, length = 0x001000
}
SECTIONS
{
codestart : > BEGIN, PAGE = 0, ALIGN(4)
.TI.ramfunc : LOAD = FLASHE,
RUN = RAMMall,
RUN_START(_RamfuncsRunStart),
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
PAGE = 0
.text :>> FLASHN | FLASHM, PAGE = 0
.cinit : > FLASHL, PAGE = 0
.pinit : > FLASHL, PAGE = 0
.switch : > FLASHL, PAGE = 0
.econst : > FLASHC, PAGE = 0
Cla1Prog : fill = 0x5555 //fill value for holes
{
.+=0x4; // empty space at head of section
*(Cla1Prog)
}
LOAD = FLASHD,
RUN = RAMLS0in1,
RUN_START(_Cla1ProgRunStart),
LOAD_START(_Cla1ProgLoadStart),
LOAD_SIZE(_Cla1ProgLoadSize),
PAGE = 0
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > RAMLS4in5, PAGE = 1
.scratchpad : > RAMLS4in5, PAGE = 1
.bss_cla : > RAMLS4in5, PAGE = 1
.const_cla : LOAD = FLASHB,
RUN = RAMLS4in5,
RUN_START(_Cla1ConstRunStart),
LOAD_START(_Cla1ConstLoadStart),
LOAD_SIZE(_Cla1ConstLoadSize),
PAGE = 1
Cla1DataRam : > RAMLS4in5, PAGE = 1
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
.cio : > RAMGS7, PAGE = 1
.sysmem : > RAMGS7, PAGE = 1
.stack : > RAMGS3in4, PAGE = 1 /* Needs to be in lower 64K memory */
.ebss : > RAMGS5in6, PAGE = 1
.esysmem : > RAMGS7, PAGE = 1
}
//#############################################################################
// End of file.
//#############################################################################
// The user must define CLA_C in the project linker settings if using the
// CLA C compiler
// Project Properties -> C2000 Linker -> Advanced Options -> Command File
// Preprocessing -> --define
CLA_SCRATCHPAD_SIZE = 0x200;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */
BEGIN : origin = 0x000000, length = 0x000002
RAMMall : origin = 0x000002, length = 0x00800
RAMD0 : origin = 0x00B000, length = 0x000800
RAMD1 : origin = 0x00B800, length = 0x000800
RAMLS0in1 : origin = 0x008000, length = 0x001000
RAMGS8do11 : origin = 0x014000, length = 0x004000
//RAMGS8 : origin = 0x014000, length = 0x001000
//RAMGS9 : origin = 0x015000, length = 0x001000
//RAMGS10 : origin = 0x016000, length = 0x001000
//RAMGS11 : origin = 0x017000, length = 0x001000
RESET : origin = 0x3FFFC0, length = 0x000002
PAGE 1 :
BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
RAMLS2in3 : origin = 0x009000, length = 0x001000
RAMLS4in5 : origin = 0x00A000, length = 0x001000
RAMGS3in4 : origin = 0x00F000, length = 0x002000
RAMGS5in6 : origin = 0x011000, length = 0x002000
RAMGS7 : origin = 0x013000, length = 0x001000
}
SECTIONS
{
codestart : > BEGIN, PAGE = 0
.TI.ramfunc : {} > RAMMall, PAGE = 0
.text : > RAMGS8do11, PAGE = 0
.cinit : > RAMMall, PAGE = 0
.pinit : > RAMD1, PAGE = 0
.switch : > RAMD1, PAGE = 0
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
.stack : > RAMD0, PAGE = 0
.ebss : > RAMGS8do11, PAGE = 0
.econst : > RAMGS8do11, PAGE = 0
.esysmem : > RAMGS8do11, PAGE = 0
/* CLA specific sections */
Cla1Prog : > RAMLS0in1, PAGE=0
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
/* The following section definition are for SDFM examples */
Cla1DataRam : > RAMLS4in5, PAGE = 1, fill=0
/* CLA C compiler sections */
//
// Must be allocated to memory the CLA has write access to
//
CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > RAMLS4in5, PAGE = 1
.scratchpad : > RAMLS4in5, PAGE = 1
.bss_cla : > RAMLS4in5, PAGE = 1
.const_cla : > RAMLS4in5, PAGE = 1
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
#include "Main.h"
void Cla_initMemoryMap(void);
void CLA_initCpu1Cla(void);
extern uint32_t Cla1ProgRunStart, Cla1ProgLoadStart, Cla1ProgLoadSize;
extern uint32_t Cla1ConstRunStart, Cla1ConstLoadStart, Cla1ConstLoadSize;
void Init_CLA(void){
//------------
#ifdef _FLASH
memcpy((uint32_t *)&Cla1ProgRunStart, (uint32_t *)&Cla1ProgLoadStart,
(uint32_t)&Cla1ProgLoadSize );
memcpy((uint32_t *)&Cla1ConstRunStart, (uint32_t *)&Cla1ConstLoadStart,
(uint32_t)&Cla1ConstLoadSize );
#endif
DELAY_US(100);
EALLOW;
CPU1_CLA1(ENABLE); //Enable CPU1.CLA module
VBUS32_1(CONNECT_TO_CLA1); //Connect VBUS32_1 (SDFM bus) to CPU1
EDIS;
Cla_initMemoryMap();
EALLOW;
CLA_initCpu1Cla();
EALLOW;
Cla1ForceTask8andWait();
WAITSTEP;
DmaClaSrcSelRegs.CLA1TASKSRCSEL1.bit.TASK1=CLA_TRIG_SD1INT; // Trigger Source for TASK1 of CLA1 = SDFM1
DmaClaSrcSelRegs.CLA1TASKSRCSEL1.bit.TASK2=CLA_TRIG_SD2INT; // Trigger Source for TASK1 of CLA1 = SDFM2
DmaClaSrcSelRegs.CLA1TASKSRCSELLOCK.bit.CLA1TASKSRCSEL1=1; // Lock CLA1TASKSRCSEL1 register
//--------------
}
void CLA_initCpu1Cla(void)
{
//
// Compute all CLA task vectors
// On Type-1 CLAs the MVECT registers accept full 16-bit task addresses as
// opposed to offsets used on older Type-0 CLAs
//
Cla1Regs.MVECT1 = (uint16_t)(&Cla1Task1);
Cla1Regs.MVECT2 = (uint16_t)(&Cla1Task2);
Cla1Regs.MVECT7 = (uint16_t)(&Cla1Task7);
Cla1Regs.MVECT8 = (uint16_t)(&Cla1Task8);
//
// Enable IACK instruction to start a task on CLA in software
// for all 8 CLA tasks
//
asm(" RPT #3 || NOP");
Cla1Regs.MCTL.bit.IACKE = 1;
Cla1Regs.MIER.all = 0x00C3;//0x0083;
//
// Configure the vectors for the end-of-task interrupt for all
// 8 tasks
//
PieVectTable.CLA1_1_INT = &Cla1Isr1;
PieVectTable.CLA1_2_INT = &Cla1Isr2;
PieVectTable.CLA1_3_INT = &Cla1Isr3;
PieVectTable.CLA1_4_INT = &Cla1Isr4;
PieVectTable.CLA1_5_INT = &Cla1Isr5;
PieVectTable.CLA1_6_INT = &Cla1Isr6;
PieVectTable.CLA1_7_INT = &Cla1Isr7;
PieVectTable.CLA1_8_INT = &Cla1Isr8;
//
// Enable CLA interrupts at the group and subgroup levels
//
//PieCtrlRegs.PIEIER11.all = 0xFFFF;
//IER |= (M_INT11 );
}
//
// Cla_initMemoryMap - Initialize Memory map
//
void Cla_initMemoryMap(void)
{
EALLOW;
//
// Initialize and wait for CLA1ToCPUMsgRAM
//
MemCfgRegs.MSGxINIT.bit.INIT_CLA1TOCPU = 1;
while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CLA1TOCPU != 1){};
//
// Initialize and wait for CPUToCLA1MsgRAM
//
MemCfgRegs.MSGxINIT.bit.INIT_CPUTOCLA1 = 1;
while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CPUTOCLA1 != 1){};
// <Step 3> : Give CLA control over program and data RAM(s)
// - The MemCfgRegs register is described in TRM 2.14.17
// Configure LS0RAM and LS1RAM as program spaces for the CLA
// First configure the CLA to be the master for LS0(1) and then
// set the spaces to be program blocks
MemCfgRegs.LSxMSEL.bit.MSEL_LS0 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS0 = 1;
MemCfgRegs.LSxMSEL.bit.MSEL_LS1 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS1 = 1;
//Next configure RAMLS2 to RAMLS5 as data spaces for the CLA
// First configure the CLA to be the master for each block and then
// set the spaces to be data blocks
MemCfgRegs.LSxMSEL.bit.MSEL_LS2 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS2 = 0;
MemCfgRegs.LSxMSEL.bit.MSEL_LS3 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS3 = 0;
MemCfgRegs.LSxMSEL.bit.MSEL_LS4 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS4 = 0;
MemCfgRegs.LSxMSEL.bit.MSEL_LS5 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS5 = 0;
}
