TMS320F28035: Adding PWM_C to HRPWM example

I haven't had the time yet to work on this issue, but will hopefully try it out later this week

Hello,

I tried looking at  this but comp sci is really not my jam..

If you could simply point out what needs to be set where, I'd greatly appreciate it. My code is below

void HRPWM_Config(period)
{
   Uint16 j;
   // ePWM channel register configuration with HRPWM
   // ePWMxA toggle low/high with MEP control on Rising edge
   EALLOW;
   SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;     // Disable TBCLK within the EPWM
   EDIS;

   for (j=1;j<4;j++)
   {
       (*ePWM[j]).TBCTL.bit.PRDLD = TB_SHADOW;             // set Shadow load
       (*ePWM[j]).TBPRD = period;                          // PWM frequency = 1/(2*TBPRD)
       (*ePWM[j]).CMPA.half.CMPA = period / 2;             // set duty 50% initially
       (*ePWM[j]).CMPA.half.CMPAHR = (0 << 8);             // initialize HRPWM extension
       (*ePWM[j]).TBPHS.all = 0;

       (*ePWM[j]).TBCTR = 0;

	   (*ePWM[j]).TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;     // Select up-down count mode
       (*ePWM[j]).TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
       (*ePWM[j]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
       (*ePWM[j]).TBCTL.bit.CLKDIV = TB_DIV1;              // TBCLK = SYSCLKOUT
       (*ePWM[j]).TBCTL.bit.FREE_SOFT = 0;

       (*ePWM[j]).CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;      // LOAD CMPA on CTR = 0
       (*ePWM[j]).CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
       (*ePWM[j]).CMPCTL.bit.SHDWAMODE = CC_SHADOW;
       (*ePWM[j]).CMPCTL.bit.SHDWBMODE = CC_SHADOW;

       (*ePWM[j]).AQCTLA.bit.CAU = AQ_SET;                 // PWM toggle high/low
	   (*ePWM[j]).AQCTLA.bit.CAD = AQ_CLEAR;
       (*ePWM[j]).AQCTLB.bit.ZRO = AQ_SET;                 // PWM toggle high/low
	   (*ePWM[j]).AQCTLB.bit.PRD = AQ_CLEAR;
	    EALLOW;
       (*ePWM[j]).HRCNFG.all = 0x0;
	   (*ePWM[j]).HRCNFG.bit.EDGMODE = HR_BEP;          // MEP control on both edges
       (*ePWM[j]).HRCNFG.bit.CTLMODE = HR_CMP;          // CMPAHR and TBPRDHR HR control
	   (*ePWM[j]).HRCNFG.bit.HRLOAD  = HR_CTR_ZERO_PRD; // load on CTR = 0 and CTR = TBPRD
       (*ePWM[j]).HRCNFG.bit.AUTOCONV = 1;              // Enable autoconversion for HR period
	   (*ePWM[j]).HRPCTL.bit.HRPE = 1;                  // Turn on high-resolution period control.
       (*ePWM[j]).TBCTL.bit.PHSEN = 1;
	   (*ePWM[j]).HRPCTL.bit.TBPHSHRLOADE = 1;          // Enable TBPHSHR sync (required for updwn count HR control)
        EDIS;
	}
    EALLOW;
    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;	// disable ePWM1 SYNC output [3]
    EPwm2Regs.TBCTL.bit.PHSEN = 1;
    EPwm2Regs.TBCTL.bit.PHSDIR = 1;				// count up after SYNC event
	EPwm2Regs.TBPHS.half.TBPHS = 2;				// initial - coarse phase offset relative to ePWM1

    SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;      // Enable TBCLK within the EPWM
    EPwm1Regs.TBCTL.bit.SWFSYNC = 1;            // Synchronize high resolution phase to start HR period

    EDIS;
}

// FreqCtlISR - interrupts at ePWM1 TBCTR = 0.
// This ISR updates the compare and period registers for ePWM modules within the same period.
__interrupt void FreqCtlISR(void)
{

    EALLOW;
	    EPwm2Regs.TBCTL.bit.PHSEN = 0;
	EDIS;


	isr_cnt++;

	   EPwm1Regs.CMPA.half.CMPA = CMPa_Reg;
       EPwm1Regs.CMPA.half.CMPAHR = CMPa_HR;         // change duty cycle

       EPwm2Regs.CMPA.half.CMPA = CMPb_Reg;
       EPwm2Regs.CMPA.half.CMPAHR = CMPb_HR;         // change duty cycle

       EPwm3Regs.CMPA.half.CMPA = CMPc_Reg;
       EPwm3Regs.CMPA.half.CMPAHR = CMPc_HR;         // change duty cycle

    // re-initialise for next PWM interrupt
	PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;   		// acknowledge PIE interrupt
	EPwm1Regs.ETCLR.bit.INT = 1;					// clear interrupt bit
}