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CCS/TMS320F28069: I2C with FIFO

Daniel Studer87
Intellectual 360 points
Part Number: TMS320F28069

Tool/software: Code Composer Studio

Hi,

I'm trying to implement i2c master operation with an EEPROM (M24LR16E-R). Because I didn't find any example code with i2c FIFO interrupts, I coded it by reference manual.

But now I have a problem with writing data to EEPROM. Reading is working fine with EEPROM, as I can see with a scope.

With this EEPROM, I can only write 4 bytes of data every 5 ms  to it. So It is very simple, when writing 4 bytes to EEPROM, I set I2CCNT to 6 (2 address bytes + 4 data bytes), and set FIFO level to 0 and start the i2c as transmitter. Then I would expect, that FIFO interrupt is occurring after 4 bytes written (2 address bytes, 2 data bytes). In FIFO interrupt I copy the last 2 bytes to I2CDXR register. After writing last 2 bytes, I should get the the stop condition detected interrupt, because 6 bytes are written (I2CCNT was set to 6).

Watching the signals with a scope gives me another behaviour. Here is a screenshot of the scope:

The yellow signal is i2c_int1a interrupt occurring, red is i2c_int2a interrupt (fifo), blue is SCL and green is SDA. Yellow and red signals are just GPIO toggles at entrance of interrupt.

As you can see, FIFO interrupt (i2c_int2a) occurres after 3 bytes written (without I2C slave address of EEPROM). As I said, in FIFO interrupt I write only 2 new bytes to I2CDXR register, but after FIFO interrupt, 3 bytes are written, then the stop condition detected interrupt is occurring (yellow). So the correct 4 bytes (containing 0, 1, 2, 3) are written to the correct address (0) of EEPROM, but the behaviour of FIFO interrupt is not as I expect.

My question is now, does the i2c slave address counts to the number of bytes that fifo has to write or not? For I2CCNT register the slave address does not count, I set it to 6 and 6 bytes are written (without i2c slave address). But I would expect, that FIFO interrupt would occur after 4 bytes and not after 3 bytes.

When I set a breakpoint in FIFO interrupt, before writing new data to I2CDXR register, the correct number of bytes are written, as you can see:

but interrupt is occurring before last byte is sent. Is that the normal behyviour?

Thanks for any help.

Regards,

Dani

  • 0
    TI__Mastermind 45206 points

    Hi Dani,

    The FIFO interrupt will trigger when the TXFFST4-0 register bits reach a value equal to or less than the TXFFIL4-0 register bits. You probably have this set to zero, so the interrupt triggers when the TX FIFO buffer (I2CDXR acts as the TX FIFO buffer) is empty. The values are shifted from I2CDXR to I2CXSR and then the byte is transmitted on SDA, see the picture below:

    I believe the FIFO buffer becomes empty, triggering the interrupt, before the byte is transmitted over the bus. You could check this by looking at the register values at the time the interrupt is triggered (TXFFST4-0 should be zero, or equal to whatever TXFFIL4-0 is set to). This shouldn't affect your application negatively since you likely want to fill the TX FIFO buffer up whenever you can.

    Hope this helps,

    Kevin