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Original question:

F28069 ADC by near ADC channels disturbance

TMS320F28379D: Internal discharge of ADC S+H capacitor

Pierre Bouchet1
Expert 2595 points
Part Number: TMS320F28379D

Hi,

I've been looking at the TINA files which show the "bleed" phenomenon where a large external capacitor will exhibit voltage drift if the external resistor's value is too high.

Namely I found two different TINA files :

  • ADCChargeShareSampleRate.TSC from here
  • PiccoloSampleRate_settling.TSC from here

In my case I'm working with a TMS320F28379D and I have several signals for which I need to make a trade-off between sample rate, accuracy, bandwidth, etc.

Hence the following question: where can I find an "official" model of the internal discharge of the ADC?

  • In ADCChargeShareSampleRate.TSC it is modeled as a 10ns discharge into a 0V source through 1Ohm, repeated at 80kHz
  • In PiccoloSampleRate_settling.TSC it is modeled as a 200ns charge to a 3.3V source through 1Ohm, repeated at 100Hz.

These two models seem to be quite different, so I don't know how to interpret this information.

Cheers,

Pierre

  • 0
    TI__Guru 60865 points
    Hi Pierre,

    Overall the simulation is to explore the trade-offs between droop/bleed error, sample rate on the simulated channel, and external resistance. ADC S+H capacitor size is also important, but is mostly fixed based on your selected design.

    *You want to make sure Ch and Ron based on the datasheet of your device.
    *The switch 'period' parameters are a simulation input that correspond to the sample rate. You change these run-to-run to see how the error changes with different sample rate.
    *Cs is selected based on your driving circuit. Probably static.
    *Rs is selected based on your driving circuit. Could be static or you may change it run-to-run to explore the trade-off between resistance and observed error.

    As far as the charging polarity:

    The major issue with this type of error is that the ADC S+H capacitor will NOT be at a known state conversion-to-conversion. It will be affected by the sequence of decisions the ADC makes in resolving the previous conversion along with the value of the previous conversion. The resulting error can therefore be systematic, but not in a predictable way. Because of this, we try and pick a worst-case starting voltage for Ch along with a worst-case forcing voltage for the ADC driver. The two options for this are (forcing V = 0V and Ch initial value = VREFHI) or (forcing V = VREFHI and Ch initial value = 0V).

    In these two simulations, two different selections were made for which case to use. Both are equally valid. I think it ends up being easier to measure the droop error with forced V = 0V because you don't need to subtract the captured voltage from the source voltage to determine the error voltage (this is the PiccoloSampleRate_settling.TSC case).
  • 0 in reply to Devin Cottier
    Expert 2595 points
    Hi Devin,

    Thanks for your answer. I have a follow-up question but I need some time to formulate it clearly.

    Regards,
    Pierre
  • 0 in reply to Pierre Bouchet1
    TI__Guru 60865 points
    Hi Pierre,

    No worries. If there isn't any activity for a week or so I'll request for the thread to be closed. You can either allow it to be closed or reply to keep it open. If it ends up closed, you can use the 'ask a related question' button to continue the discussion.