• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 82 subscribers
  • Views 598 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28035: F28035 Configuration Questions

Brian Wang0
Expert 5310 points
Part Number: TMS320F28035

Hi team,

Recently I am working with a customer on their HRPWM configurations. And I have the following questions to confirm with you:

1.  In P26 of SPRUGE8E, it mentioned:

CMPCTL[LOADAMODE]
– In up-count mode:CMPCTL[LOADAMODE] = 1 (load on CTR = PRD)
– In up-down count mode: CMPCTL[LOADAMODE] = 2 (load on CTR=0 or CTR=PRD)

Is it necessary to load on CTR=0 or CTR=PRD when using up-down count mode?

2. In the same page, you mentioned:

For TBPHS: TBPHSHR synchronization with high-resolution period, set both HRPCTL[TBPHSHRLOADE] = 1 and TBCTL[PHSEN] = 1.

 In up-down count mode these bits must be set to 1 regardless of the contents of TBPHSHR.

The description of TBPHSHRLOADE register mentioned：This bit and the TBCTL[PHSEN] bit must be set to 1 when high-resolution period is enabled for up-down count mode even if TBPHSHR = 0x0000. This bit does not need to be set when only high-resolution duty is enabled.

my question is:

1) If both HR phase and period are used, do we have to set TBCTL[PHSEN] and HRPCTL[TBPHSHRLOADE] ?

2) If only HR period is used, do we have to TBCTL[PHSEN] and HRPCTL[TBPHSHRLOADE] ?

3. We did not fully understand the point of this note.

1) To avoid the jitter, the SYNCOSEL must be set to 0 when HR period mode is enabled, is it correct? 

1) In our example code, a software sync is always performed during the initialization. Is it necessary to do this?

2) If TBCTL[SYNCOSEL] != 0 , is a software sync still necessary?

 

4. During the experiment, we noticed a one-system-clock period change on the PWM. Here is our configuration:

   EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;

   EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;

    EPwm1Regs.HRCNFG.all = 0x0;

    EPwm1Regs.HRCNFG.bit.EDGMODE = HR_BEP;   
    EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP;  
    EPwm1Regs.HRCNFG.bit.HRLOAD  = HR_CTR_ZERO_PRD;  
    EPwm1Regs.HRCNFG.bit.AUTOCONV = 1;  
    EPwm1Regs.HRPCTL.bit.HRPE = 1;
    EPwm1Regs.TBCTL.bit.PHSEN = 1;
    EPwm1Regs.HRPCTL.bit.TBPHSHRLOADE = 1;

    Do you have any idea of how to eliminate?

Sorry for having so much questions, thanks for your support.

  • 0
    TI__Mastermind 42195 points

    Wieqi,

    1. When using the HR enhancments the internal registers only get loaded on CTR=0 for this reason you should center your pulses around CTR=PRD and do not use CTR=PRD to update the values.
    2. For 1 and 2, how are you trying to configure the HRPWM? 
      For the question on jitter, a single sync pulse is fine. Do this is your systems requires it. If you then re-sync you may get a small jitter because the sync chain operates in the SYSCLK domain, not in HR domain. Thus if you configure your HRPWM to re-sync every cycle then you will see a small constant jitter each cycle.
    3. What do you mean by " one-system-clock period change on the PWM."?

    Thanks,
    Cody

  • 0 in reply to Cody Watkins
    TI__Expert 5310 points

    Hi Cody, 

    Thanks for you reply. However, I cannot fully understand your answer, here is my questions:

    1. When using the HR enhancments the internal registers only get loaded on CTR=0 for this reason you should center your pulses around CTR=PRD and do not use CTR=PRD to update the values.

    According to my understanding, you are suggesting the configuration of CMPCTL[LOADAMODE] does not work when using HR enhancements since the internal registers only get loaded on CTR=0. Thus, we do not need to follow the following note, is that correct?

    CMPCTL[LOADAMODE]
    – In up-count mode:CMPCTL[LOADAMODE] = 1 (load on CTR = PRD)
    – In up-down count mode: CMPCTL[LOADAMODE] = 2 (load on CTR=0 or CTR=PRD)

    2. For 1 and 2, how are you trying to configure the HRPWM?

    My question is:

    1) If both HR phase and period are used, do we have to set TBCTL[PHSEN] and HRPCTL[TBPHSHRLOADE] ?

    2) If only HR period is used, do we have to TBCTL[PHSEN] and HRPCTL[TBPHSHRLOADE] ?

    This is not clear in our data sheet.

     

    For the question on jitter, a single sync pulse is fine. Do this is your systems requires it. If you then re-sync you may get a small jitter because the sync chain operates in the SYSCLK domain, not in HR domain. Thus if you configure your HRPWM to re-sync every cycle then you will see a small constant jitter each cycle.

    According to the TRM, TBCTL[SYNCOSEL] must be 0 if HR period is enabled to avoid the jitter.

    Then, how should we configure the ePWM to sync is we need a changing frequency control? Since changing frequency control requires

    sync every cycle, how to avoid the jitter?

     

    3.  What do you mean by " one-system-clock period change on the PWM."?

    I will work with customer to get the waveform and post it later.

    Thanks,

    Cody

  • 0 in reply to Brian Wang0
    TI__Mastermind 42195 points

    Weiqi,

    Weiqi Wang said:
    According to my understanding, you are suggesting the configuration of CMPCTL[LOADAMODE] does not work when using HR enhancements since the internal registers only get loaded on CTR=0. Thus, we do not need to follow the following note, is that correct?

    My comments were specifically for Up-down count mode, and in that mode you should load on CTR=0.

    Weiqi Wang said:
    1) If both HR phase and period are used, do we have to set TBCTL[PHSEN] and HRPCTL[TBPHSHRLOADE] ?

    Yes.

    Weiqi Wang said:
    2) If only HR period is used, do we have to TBCTL[PHSEN] and HRPCTL[TBPHSHRLOADE] ?

    Yes, if you are using Up-down count mode. Yes, if you wish to maintain a phase relationship between multiple PWMs.

    If you need phase control between 2 separate HRPWMs there will be some jitter on a F28035 device. It will be 1 or 2 cycles. On newer devices  we have added the TRREM register to remove this jitter when syncing HRPWMs. You will need to determine if the jitter is acceptable for your system.


    Regards,
    Cody