Hello,
I've already successfully used EPWM1,2,3,4,5,6,8 at the same time. All them with similar configuration. Applying the same configuration to EPWM10 doesn't give correct results.
The deadband configuration used with other pwms doesn't work with this one, Also the count compare functionality fails to give the correct pulse size. I have no idea what is going on.
I have a pulse. The pulse change when I change the value, but the pulse size result is no correct. I verified the register values and all seems to be ok. One example code is attached.
void InitEPwm10Gpio(void)
{
EALLOW;
GpioCtrlRegs.GPAPUD.bit.GPIO18 = 1; // Disable pull-up on GPIO163 (EPWM10A)
GpioCtrlRegs.GPAPUD.bit.GPIO19 = 1; // Disable pull-up on GPIO164 (EPWM10B)
GpioCtrlRegs.GPAGMUX2.bit.GPIO18 = 1;
GpioCtrlRegs.GPAGMUX2.bit.GPIO19 = 1;
GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Disable pull-up on (EPWM10A)
GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Disable pull-up on (EPWM10B)
EDIS;
}
#define PWM1_PERIOD 2000 // #define PWM1_CMPR25 PWM1_PERIOD>>2 // PWM1 initial duty cycle = 25% // Variables Uint16 dutyCycle_a = PWM1_CMPR25; // PWM1 duty cycle = 25% Uint16 dutyCycle_b = PWM1_CMPR25; // PWM1 duty cycle = 25% Uint16 dutyCycle_g = PWM1_CMPR25; // PWM5 duty cycle = 25% Uint16 dutyCycle_h = PWM1_CMPR25; // PWM5 duty cycle = 25% Uint16 dutyCycle_c = PWM1_CMPR25; // PWM5 duty cycle = 25% Uint16 dutyCycle_d = PWM1_CMPR25; // PWM5 duty cycle = 25% Uint16 dutyCycle_e = PWM1_CMPR25; // PWM5 duty cycle = 25% Uint16 dutyCycle_f = PWM1_CMPR25; // PWM5 duty cycle = 25%
void main(void) { // Initialize System Control InitSysCtrl(); EALLOW; ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = TB_DIV1; EDIS; // Initialize GPIO Primary side InitGpio(); // Configure default GPIO InitEPwm1Gpio(); // Configure EPWM1 GPIO pins InitEPwm2Gpio(); // Configure EPWM2 GPIO pins InitEPwm3Gpio(); // Configure EPWM3 GPIO pins InitEPwm10Gpio(); // Configure EPWM10 GPIO pins // Initialize GPIO Secondary side InitEPwm4Gpio(); InitEPwm5Gpio(); // Configure EPWM5 GPIO pins InitEPwm6Gpio(); // Configure EPWM6 GPIO pins InitEPwm8Gpio(); // Configure EPWM8 GPIO pins EALLOW; GpioCtrlRegs.GPADIR.bit.GPIO31 = 1; // Drives LED LD2 on controlCARD EDIS; GpioDataRegs.GPADAT.bit.GPIO31 = 1; // Turn off LED // Clear all interrupts and initialize PIE vector table DINT; InitPieCtrl(); IER = 0x0000; IFR = 0x0000; InitPieVectTable(); // Map ISR functions EALLOW; PieVectTable.ADCA1_INT = &adca1_isr; // Function for ADCA interrupt 1 EDIS; // Configure the ADC and power it up ConfigureADC(); // Setup the ADC for ePWM triggered conversions on channel 0 SetupADCEpwm(); // Initialize ePWM modules InitEPwm1(); InitEPwm2(); InitEPwm3(); InitEPwm10(); InitEPwm4(); InitEPwm5(); InitEPwm6(); InitEPwm8(); // Initialize results buffers for(resultsIndex = 0; resultsIndex < RESULTS_BUFFER_SIZE; resultsIndex++) { AdcaResults[resultsIndex] = 0; AdccResults[resultsIndex] = 0; } resultsIndex = 0; // Enable global interrupts and higher priority real-time debug events IER |= M_INT1; // Enable group 1 interrupts EINT; // Enable Global interrupt INTM ERTM; // Enable Global realtime interrupt DBGM // Enable PIE interrupt PieCtrlRegs.PIEIER1.bit.INTx1 = 1; // Sync ePWM EALLOW; CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; do { GpioDataRegs.GPADAT.bit.GPIO31 = 0; // Turn on LED DELAY_US(1000 * 500); // ON delay GpioDataRegs.GPADAT.bit.GPIO31 = 1; // Turn off LED DELAY_US(1000 * 500); // OFF delay } while(1); } interrupt void adca1_isr(void) { // execute the control code here exec(); // Update duty cycles and phase-shift. Max and min values for duty cycle are 1900 and 100. EPwm1Regs.CMPA.bit.CMPA = dutyCycle_a; EPwm2Regs.CMPA.bit.CMPA = dutyCycle_b; EPwm3Regs.CMPA.bit.CMPA = dutyCycle_g; EPwm10Regs.CMPA.bit.CMPA = dutyCycle_h; EPwm4Regs.CMPA.bit.CMPA = dutyCycle_c; EPwm4Regs.TBPHS.bit.TBPHS = phi; EPwm5Regs.CMPA.bit.CMPA = dutyCycle_d; EPwm5Regs.TBPHS.bit.TBPHS = phi + GRAD_180; EPwm6Regs.CMPA.bit.CMPA = dutyCycle_f; EPwm6Regs.TBPHS.bit.TBPHS = phi + GRAD_90; EPwm8Regs.CMPA.bit.CMPA = dutyCycle_e; EPwm8Regs.TBPHS.bit.TBPHS = phi + GRAD_90; // Return from interrupt AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; // Clear ADC INT1 flag PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge PIE group 1 to enable further interrupts // store results AdcaResults[resultsIndex] = AdcaResultRegs.ADCRESULT0; if(RESULTS_BUFFER_SIZE <= resultsIndex) { resultsIndex = 0; } } void InitEPwm1(void) { // Setup TBCLK EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;// Count up and down EPwm1Regs.TBPRD = PWM1_PERIOD; // Set timer period EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0 EPwm1Regs.TBCTR = 0x0000; // Clear counter EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // SYNC output on CTR = 0 // trip EPwm1Regs.TZCTL.bit.TZA = 2; // force low state for PWMA and PWMB EPwm1Regs.TZCTL.bit.TZB = 2; // Setup shadow register load on ZERO EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // Deadband control EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL; EPwm1Regs.DBRED.bit.DBRED = 10; EPwm1Regs.DBFED.bit.DBFED = 10; // Set Compare values EPwm1Regs.CMPA.bit.CMPA = dutyCycle_a; // Set compare A value // Set actions EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Enable ADC sync SOCA EPwm1Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group EPwm1Regs.ETSEL.bit.SOCASEL = 2; // Select SOCA, 0b100: Enable event time-base counter equal to CMPA when the timer is incrementing or CMPC when the timer is incrementing // 2 (TBCTR =TBPRD EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOCA EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event // Enable ADC sync SOCA EPwm1Regs.ETSEL.bit.SOCBEN = 0; // Disable SOC on A group EPwm1Regs.ETSEL.bit.SOCBSEL = 1; // Select SOCA, 0b100: Enable event time-base counter equal to CMPA when the timer is incrementing or CMPC when the timer is incrementing // 2 (TBCTR =TBPRD) 1 (TBCTR =0) EPwm1Regs.ETSEL.bit.SOCBEN = 1; // Enable SOCA EPwm1Regs.ETPS.bit.SOCBPRD = 1; // Generate pulse on 1st event } void InitEPwm2(void) { // Setup TBCLK EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;// Count up and down EPwm2Regs.TBPRD = PWM1_PERIOD; // Set timer period EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading EPwm2Regs.TBPHS.bit.TBPHS = GRAD_180; // Phase is 180 EPwm2Regs.TBCTR = 0x0000; // Clear counter EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // SYNC output on CTR = 0 // trip EPwm2Regs.TZCTL.bit.TZA = 2; // force low state for PWMA and PWMB EPwm2Regs.TZCTL.bit.TZB = 2; // Setup shadow register load on ZERO EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // Dead band control EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL; EPwm2Regs.DBRED.bit.DBRED = 10; EPwm2Regs.DBFED.bit.DBFED = 10; void InitEPwm10(void) { // Setup TBCLK EPwm10Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;// Count up and down EPwm10Regs.TBPRD = PWM1_PERIOD; // Set timer period EPwm10Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading EPwm10Regs.TBPHS.bit.TBPHS = 0; // Phase is 90 = 0 (PWM1) + 90 EPwm10Regs.TBCTR = 0x0000; // Clear counter EPwm10Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT EPwm10Regs.TBCTL.bit.CLKDIV = TB_DIV1; EPwm10Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // SYNC output on CTR = 0 // trip EPwm10Regs.TZCTL.bit.TZA = 2; // force low state for PWMA and PWMB EPwm10Regs.TZCTL.bit.TZB = 2; // Setup shadow register load on ZERO EPwm10Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO EPwm10Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; EPwm10Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; EPwm10Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // Deadband control EPwm10Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; EPwm10Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; EPwm10Regs.DBCTL.bit.IN_MODE = DBA_ALL; EPwm10Regs.DBRED.bit.DBRED = 10; EPwm10Regs.DBFED.bit.DBFED = 10; // Set Compare values EPwm10Regs.CMPA.bit.CMPA = dutyCycle_h; // Set compare A value // Set actions EPwm10Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero EPwm10Regs.AQCTLA.bit.CAD = AQ_CLEAR; }
