hello, I meat a problem when setup the SDRAM MT48LC16M16A2, 8192 rows by 512 columns by 16 bits.
I am not sure about following setup, which comes from ti example:
//
//Tref = 64ms for 8192 ROW, RR = 64000*100(Tfrq)/8192 = 781.25 (0x30E)
//
Emif1Regs.SDRAM_RCR.all = 0x30E;
//
//PAGESIZE=2 (1024 elements per ROW), IBANK = 2 (4 BANK), CL = 3,
//NM = 1 (16bit)
//
Emif1Regs.SDRAM_CR.all = 0x00015622;
should the pagesize be 8192 according to the SDRAM spec? well, I only find PAGESIZE=3 (2048) choice in the F28379D docs. Is that means the SDRAM actually not compatible with F28379D ?
