Prefetched buffer H0~5 Memory in TMS320C28346

yeunhun choi said:

Is it  related Instruction pipline ? (Does it mean that I should all most code in Hx area to speed up?)

Is it buffer to compensate slow access memory(H0~H5 : 1 wait)?

The H0-H5 memories are 1 wait state as you noted.  This means anytime the memory is accessed it takes 2 cycles.  

In order to improve performance of any code that executes from this memory a pre-fetch buffer has been added.  With the prefetch buffer more than one instruction will be read from the memory at a time.   The contents of this pre-fetch buffer are then sent to the CPU for processing as required. During the time it takes to process these instructions, the RAM pipeline automatically initiates another access to the memory in order to pre-fetch the next set of instructions. Using this technique, the overall efficiency of sequential code execution is improved.

Code that is most time critical should be executed in memory that is zero waitstate.

-Lori