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TMS320F28377D: Triggering scheme SPI/DMA for external ADC

Mike Twieg
Intellectual 960 points

Part Number: TMS320F28377D

Hi all, I'm trying to interface a F28377D to an external 16b ADC (LTC2378-16), goal is to have the result available in RAM within 1us of triggering a conversion. Overall I'm looking at a scheme very similar to that described in this post, though I intend to use the normal SPI instead of McBSP (since SPI can operate up to 50MHz in high speed mode). I intend to generate the CNV pulses using ePWM.

In the linked example, the author uses two DMA channels, first to start the SPI transaction (triggered via XINT by the ADC's busy signal) and another to move the received data to RAM. My question is if there is an alternative that doesn't require using a valuable DMA channel to trigger a dummy transition. Is it perhaps possible to trigger the SPI via XINT, or by a PWM event? Software triggering using an interrupt is not an option here.

  • 0
    TI__Guru 55700 points
    Mike,

    External interrupt (or) PWM event interrupt doesn't automatically trigger a SPI transaction unless it is initiated in software in XINT ISR (or) PWM ISR routine.

    Regards,
    Manoj
  • 0 in reply to Manoj Santha Mohan
    Intellectual 960 points
    Hi Manoj, I figured as much... If I need to invoke the DMA, then I have a second concern:

    I need the ADC conversion to be available to the CLA (either in the message RAM or the CLA RAM). It's my understanding that using the SPI with DMA will require connecting the DMA to Peripheral Frame 2 bridge (CpuSysRegs.SECMSEL.bit.PF2SEL = 1). But if I do so, won't prevent the CLA from directly accessing the SPI RX FIFO? And since the DMA can't access any CLA RAM, I can't use it to transfer the result directly.
  • 0 in reply to Mike Twieg
    TI__Guru** 117001 points

    Hi Mike,

    I need the ADC conversion to be available to the CLA (either in the message RAM or the CLA RAM). It's my understanding that using the SPI with DMA will require connecting the DMA to Peripheral Frame 2 bridge (CpuSysRegs.SECMSEL.bit.PF2SEL = 1). But if I do so, won't prevent the CLA from directly accessing the SPI RX FIFO? And since the DMA can't access any CLA RAM, I can't use it to transfer the result directly.

    Your understanding is correct. If you are enabling the DMA access to SPI then CLA will not be able to access SPI and there is no RAM shared between DMA and CLA. So in this case you may have to let CLA access the SPI RX data buffer instead of DMA and have CPU initiate the SPI based on XINT event. Or have the CPU copy the data from shared RAM to LSx RAM (for CLA to access) after DMA copies the data there (based on DMA done interrupt).

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Intellectual 960 points
    CPU1 is already running a critical control loop, so I absolutely can't add another ISR to CPU1, either to initiate the SPI TX or to move the data to CLA RAM. There are a couple workarounds I have in mind which take advantage of the fact that both the CPU ISR and the CLA task have the same trigger, so they execute synchronously.

    And I'm assuming the CLA can't access SECMSEL, right?
  • 0 in reply to Mike Twieg
    TI__Guru 55700 points

    CLA doesn't have access to SECMSEL register.

    Regards,

    Manoj