CCS/TMS320F28335: context saved when enter interrupt,disassembly code

Hello Richard,

   Thanks for your reply!

  In my project of motor control, I write a scheduler to run the 8 tasks. The frequency of some tasks executed are

more than I expected.For example, in one second, task 4 should be executed 1000 times, but it be executed more than

1000 times, sometimes it is 1003 times,sometimes it is 1005 times, the executed times is not  constant, but I am

sure it is larger than 1000.

 In my code, I disabling the global interrupt mask at times because of the critical code, and when these critical

code are executed,I enabled he global interrupt mask at once.These doesn,t influence on the frequency of task

executed.

 Dear Richard, I have spent a lot of time on this issue,but I can not find the bug,please help me.I guess there is

something wrong with the compiler.If you need the project code,I can send you by email.

 Today, I do some test,the test results are as following,

When task 3 is entered, a gpio(channel 2) is set, and when task 3 is finished(is executed completely),the gpio(channel 2) is drived low, task 3's period is 1ms.From the first attchment,we can see task 3 is executed twice,and the blank time is 600ns，It should be 1ms just as the second attachment.

Please take some time to review my code,Thanks!

Best regards,

Victor

Victor,

Some questions:

 - what is channel 1 in the two oscilloscope plots you sent?

 - what is triggering task 3?  Do you have a hardware timer set up and if so, which one?

Regards,

Richard

Dear Richard,

- what is channel 1 in the two oscilloscope plots you sent?

I show task 3 code as follows,

if(rtTaskTimer[3].flag)

{

DTS1 = 1;
if(taskBusyStatus.word&0x0007)
{
       return;
}
DINT;
rtTaskTimer[3].flag = 0;
if(taskBusyStatus.bit.task3Busy)
{
       taskReenStatus.bit.task3Reen = 1;
}
else
{
       taskBusyStatus.bit.task3Busy = 1;
}
EINT;
DTS2 = 1;
count1++;
//task 3......
//............
//............
DTS2 = 0;
DINT;
taskBusyStatus.bit.task3Busy = 0;
EINT;
DTS1 = 0;

}

channel one is sent by gpio DTS1 and channel 2 is sent by gpio DTS2.From above two pictures,Plots on first picture

are wrong and it occurs occasionally.Plots on second picture are right.

rtTaskTimer[3].flag is set in the task 0(its priority is highest) and cleared in task 3
taskBusyStatus.word&0x0007 is for detecting Whether there are higher priority tasks


- what is triggering task 3? Do you have a hardware timer set up and if so, which one?

There is a task(its priority is highest and its executed period is 62.5us) is triggered by hardware timer.
In fact,there are two interrupt sources for the task,EPwm1 is ET_CTR_ZERO interrupt and EPwm2 is ET_CTR_PRD interrupt,their periods are both 125us.So the task is executed on every 62.5us. 

The configuration is as follow,
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.EPWM1_INT = &epwm_timer_isr;
PieVectTable.EPWM2_INT = &epwm_timer_isr;
EDIS;

void F281X_EV1_PWM_Init(PWMGEN *p)
{
// Enable TZ1 as one shot trip sources
EALLOW;
EPwm1Regs.TZSEL.bit.OSHT3 = 1;
EPwm2Regs.TZSEL.bit.OSHT3 = 1;
EPwm3Regs.TZSEL.bit.OSHT3 = 1;
EPwm4Regs.TZSEL.bit.OSHT3 = 1;
// What do we want the TZ1 to do?
EPwm1Regs.TZCTL.bit.TZA = TZ_HIZ;
EPwm1Regs.TZCTL.bit.TZB = TZ_HIZ;
EPwm2Regs.TZCTL.bit.TZA = TZ_HIZ;
EPwm2Regs.TZCTL.bit.TZB = TZ_HIZ;
EPwm3Regs.TZCTL.bit.TZA = TZ_HIZ;
EPwm3Regs.TZCTL.bit.TZB = TZ_HIZ;
EPwm4Regs.TZCTL.bit.TZA = TZ_NO_CHANGE;
EPwm4Regs.TZCTL.bit.TZB = TZ_NO_CHANGE;
// Enable TZ interrupt
EPwm4Regs.TZEINT.bit.OST = 1;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Stop all the TB clocks
EDIS;
//=====================================================================
// Initialization Time
//========================// EPWM Module 1 config
EPwm1Regs.TBPRD = p->PeriodMax; // Period = 1600 TBCLK counts
EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; // /1
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Master module
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero/Period
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero/Period
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // set actions for EPWM1A
EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm1Regs.DBFED = DBTIME;//350; 4.8us // FED = 50 TBCLKs
EPwm1Regs.DBRED = DBTIME;//350; 4.8us // RED = 50 TBCLKs
//EPWM Module 2 configuration
EPwm2Regs.TBPRD = p->PeriodMax; // Period = 1600 TBCLK counts
EPwm2Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode
EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0; // /1
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero/Period
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero/Period
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // set actions for EPWM2A
EPwm2Regs.AQCTLA.bit.CAD = AQ_SET;
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm2Regs.DBFED = DBTIME;//350; //4.8us // FED = 50 TBCLKs
EPwm2Regs.DBRED = DBTIME;//350; //4.8us // RED = 50 TBCLKs
//EPWM Module 3 configuration
EPwm3Regs.TBPRD = p->PeriodMax; // Period = 1600 TBCLK counts
EPwm3Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode
EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0; // /1
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero/Period
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero/Period
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; // set actions for EPWM3A
EPwm3Regs.AQCTLA.bit.CAD = AQ_SET;
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm3Regs.DBFED = DBTIME; //4.8us // 2.4us

//FED = 50 TBCLKs
EPwm3Regs.DBRED = DBTIME; //350;

//4.8us // 2.4us RED = 50 TBCLKs
//Run Time (Note: Example execution of one run-time instant)
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event

EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_PRD; // Enable INT on Period event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event

//ADC trigger
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOCA
EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO; // Generate SOCA pulse on zero
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st

event

EPwm2Regs.ETSEL.bit.SOCAEN = 1; // Enable SOCA
EPwm2Regs.ETSEL.bit.SOCASEL = ET_CTR_PRD; // Generate SOCA pulse on period
EPwm2Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st

event

EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // do not Start all the

timers synced
EDIS;
p->mFuncLmt = 31130; // 31130 95%
}


and in this task,there is a function,it is executed on every 62.5us and its code is as follow


void rtTaskTimerUpdate()
{
       int16 i;
      for(i=0;i<RTTASK_TIMERNUM;i++)
     {
          if(rtTaskTimer[i].counter < rtTaskTimer[i].period)
          {
              rtTaskTimer[i].counter++;
         }
        else
        {
             rtTaskTimer[i].flag = 1;
             rtTaskTimer[i].counter = 0;
        }
    }
 }
when rtTaskTimer[i].flag is set,it represent the corresponding should be executed.

task 3 is triggered by rtTaskTimer[3].flag

Hope your detailed answer sincerely!
Best regards,
Victor

Dear Richard,

I have done these experiments,

- Disable one interrupt trigger, for example EPwm2Regs.ETSEL.bit.INTEN = 0; then run it. Your tasks should run at half the rate, but do you still see the issue?

The issue doesn't occur when the interrupt period is 125us.But when I  set the interrupt period as 62.5us,this issue occurs again, it represent this issue is relevant to the cpu load,when the cpu load is heavy, many tasks are interrupted,and the stack is used heavily.

- Write a separate and identical ISR for ePWM2. Does the issue go away?

This issue still occurs.

Richard, I think there is someting wrong with the compiler. This scheduler was good when I run it on Tms320lf2407 many years age,at that time I wrote this scheduler in assemble language.

But TMS320F28X‘s assemble language is too complicated, I cann't write this scheduler in assemble language in a short time and this project is a little urgent.Can you help to study the disassebly,Maybe the issue  can be found easily.  Thank  you very much.

Moreover, Not just task 3, but sometimes several tasks have  this issue.

attached is the demo code. 

BR

Victor

When you ran with a period of 125 us, was it from changing the actual period of the PWM or did you disable the ePWM2 interrupt as Richard suggested?

The first scope capture you shared looks like it might be the EPWM ISR being preempted by the EPWM ISR (probably at the EINT; before the DTS2 = 1;). Do you want it to be able to do that? I see you're re-enabling group 3 at the start of the ISR, so I assume so...?

Whitney

Whitney and Richard,

-When you ran with a period of 125 us, was it from changing the actual period of the PWM or did you disable the ePWM2 interrupt as Richard suggested?

When I ran with a period of 125us, I disabled the epwm2 interrupt, only epwm1 interrupt was working. In fact ,in my system, there are two interrupt sources, one is  EPwm1  ET_CTR_ZERO interrupt and the other is EPwm2 ET_CTR_PRD interrupt, the periods of the two interrputs are both 125us, and the two interrupt executes the same code. If the two interrupts are working together, then the period is 62.5us.

if I disabled one of the two interrputs, then the executed period of code is 125us. in the condition above, I can not find the issue

I have do another experiment, only EPWM1 interrupt is enabled and I change PWM switching frequency from 8Khz to 16KHz, the issue occur again.

it represent this issue is relevant to the cpu load,when the cpu load is heavy, many tasks are interrupted,and the stack is used heavily.

-The first scope capture you shared looks like it might be the EPWM ISR being preempted by the EPWM ISR (probably at the EINT; before the DTS2 = 1;). Do you want it to be able to do that? I see you're re-enabling group 3 at the start of the ISR, so I assume so...?

In my code,EPWM ISR can be preempted by itself. there are 8 tasks in my system,

and task 0(period is 62.5us) should be completed in 62.5us,

task 1(period is 125us) should be completed in 125us and it can be preempted by task 0,

task 2(period is 250us) should be completed in 250us and it can be preempted by task 0 and task 1

task 3(period is 625us) should be completed in 250us and it can be preempted by task 0 ,task 1,task 2

task 4(period is 1ms) should be completed in 250us and it can be preempted by task 0 ,task 1,task 2 ,task 3

task 5(period is 10ms) should be completed in 250us and it can be preempted by task 0 ,task 1,task 2 ,task 3,task 4

task 6(period is 330s) should be completed in 250us and it can be preempted by task 0 ,task 1,task 2 ,task 3,task 4 ,task 5

task 7(period is 1s) should be completed in 1s and it can be preempted by task 0 ,task 1,task 2 ,task 3,task 4 ,task 5 and task 6

If any task can not be  completed in the corresponding time,system would report error.

The phenomenon is too strange and illogical.

and demo code I have upload,please take some time to review.

I need your help!!!

BR

Victor