Compiler/TMS320F28379D: Leaving the pwm output when changing the phase (between epwm1 and epwm2) shift between are 0-90° to area 90°-180° .

Part Number: TMS320F28379D

Tool/software: TI C/C++ Compiler

Hello,
I encounter a jump of pwm during the evolution of the phase shift control of the zone 0-90 ° to 90 ° -180 °.

Here is the config of my timer:
//
// ConfigureEPWM1 ​​- Configure EPWM SOC and compare values
//
void ConfigureEPWM1 ​​(void)
{
    EALLOW;

    // Assumes ePWM clock is already enabled
    //EPwm1Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group
    //EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC on up-count
    //EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event

    EPwm1Regs.TBPRD = Period_Consigne; // Set period to 4096 counts
    EPwm1Regs.CMPA.bit.CMPA = Period_Consigne / 2; // Set compare A value to 2048 counts
    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // up / down counter

    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; // LOAD CMPA on CTR = 0
    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;
    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

    EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Master module
    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module

// EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // Set PWM1A on Zero
    EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A compares A in Up-mode
    EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A compares A in Down-mode
// EPwm1Regs.AQCTLA.bit.PRD = AQ_SET; // Set PWM1A on Zero

    // Interrupt where we will change the Deadband
    EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
// (* ePWM [j]). ETSEL.bit.INTSEL = ET_CTRU_CMPA; // Select INT on CMPA event
    EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
    EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1rt event

    EDIS;
}

//
// ConfigureEPWM1 ​​- Configure EPWM SOC and compare values
//
void ConfigureEPWM2 (void)
{
    EALLOW;

    // Assumes ePWM clock is already enabled
    //EPwm1Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group
    //EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC on up-count
    //EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event

    EPwm2Regs.TBPRD = Period_Consigne; // Set period to 4096 counts
    EPwm2Regs.CMPA.bit.CMPA = Period_Consigne / 2; // Set compare A value to 2048 counts
    EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // up / down counter

    EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; // LOAD CMPA on CTR = 0
    EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;
    EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

    EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
    EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Sync flow-through

    EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // Set PWM1A on Zero
    EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A compares A in Up-mode
    EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A compares A in Down-mode
    EPwm2Regs.AQCTLA.bit.PRD = AQ_SET; // Set PWM1A on Zero

    EDIS;
}

as well as the modification of the phase of the timer 2 in the interruption of timer 1:

interrupt void epwm1_isr (void)
{
    //
    // Clear INT flag for this timer
    //
    EPwm1Regs.ETCLR.bit.INT = 1;
    if (GPIO_ReadPin (31)) GPIO_WritePin (31,0); else GPIO_WritePin (31,1);

    if (Counter <20)
    {
        Counter ++;
    }
    else
    {
        Counter = 0;
        Out + = sense;
/ *
        // Avoid the 90 ° zone
        if (((Periode_Consigne / 2-Increment) <Out) && (Out <(Period_Consigne / 2 + Increment)))
        {
          if (direction> = 0) Out = Period_Consigne / 2 + Increment;
          else Out = Periode_Consigne / 2-Increment;
        }
        else if (((-Periodic_Consigne / 2-Increment) <Out) && (Out <(-Periodic_Consigne / 2 + Increment)))
        {
          if (direction> = 0) Out = -Periodic_Consigne / 2 + Increment;
          else Out = -Periodic_Consigne / 2-Increment;
        }
* /
        // if (Out <- (2 * Period_Consigne)) {sense = + 1; Out = -2 * Period_Consigne;}
        // else if (Out> (2 * Periode_Consigne)) {sense = -1; Out = 2 * Periode_Consigne;}
        if (Out <- (1 * Period_Consigne)) {sense = + 1; Out = -1 * Period_Consigne;}
        else if (Out> (1 * Periode_Consigne)) {sense = -1; Out = 1 * Periode_Consigne;}
    }

    if (Out> 0)
     {
      EPwm2Regs.TBCTL.bit.PHSDIR = TB_DOWN;
      EPwm2Regs.TBPHS.bit.TBPHS = Out;
     }
    else
     {
      EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP;

     EPwm2Regs.TBPHS.bit.TBPHS = -Out;
      }

    //
    // Acknowledge this interrupt to receive more interrupts from group 3
    //
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}