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TMS320F2812- Watch dog

Jeffery Day
Expert 3605 points

Customer is asking:

requeset clarification of watchdog behavior: 1. data sheet mentions a HALT state that will stop the watchdog. cannot find any reference in the document to how this HALT state occurs. 2. could the HALT state occur due to single- event-upsets or code getting lost during normal operation, and lead to watchdog not being able to reset the DSP? 3. for high-reliablity designs, should we implement an external watchdog circuit?

Regards,

Jeff

  • 0
    TI__Expert 8500 points

    Jeff,

    HALT mode stops all clocks, including shutting down the crystal oscillator. The operation is described in Chapter 3 of the System Control Reference Guide (http://www.ti.com/litv/pdf/spru078f). Two things have to occur for this to happen, 1) the LPMCR0 register has to be set to put the processor into the HALT state when an IDLE instruction is executed (the alternatives IDLE and STANDBY do not stop the WD), and 2) the CPU must execute the IDLE instruction. The probability of two errors occurring is usually considered low enough to not protect against, even in safety critical applications. Furthermore, the LPMCR0 register is EALLOW protected, so actually a third thing has to occur prior to #1 above - the EALLOW instruction must be executed.

    Regards,
    Dave Foley