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TMS320F280049: DCSM and GRABRAM/GRABSECT usage

Wesley C
Intellectual 925 points
Part Number: TMS320F280049
Other Parts Discussed in Thread: TMS320F28377S, , C2000WARE

Hi,

I'm looking for a bit of an explanation about the DCSM on the TMS320F280049  (and later on the TMS320F28377S).

Right now I've perused the technical documentation and looked through the forums, but I'm still a bit confused regarding the Zone blocks and the GRABRAM or GRABSECT registers within the DCSM's user OTP.

Regarding the 3.13 section of SPRUI33A, I see that table 3-15 indicates that 2 bits of these registers are used to indicate whether a particular RAM block or Flash sector is part of Zone 1, Zone 2, or unsecure.

Looking through the C2000Ware f28004x_driverlib project, I've found a file with defines that seem to partition these registers for the 2 bits aligning with the available Flash sectors (GRABSECT) or RAM blocks (GRABRAM).

I have a number of questions regarding this.

  • Why does each block in the Bank0 and Bank1 Zone have an associated register allocation for GRABSECT and GRABRAM?
  • Further, why does the DSCM have multiple blocks per zone? Is this so that you can configure certain memories for special purposes (execonly, etc)?
  • Can I use just a few blocks or are they tied to specific purposes?

My previous experience with the CSM with an older Delfino was that setting the CSM registers would lock all the secure memories. It appears that there is a lot more flexibility in the CSMs of recent chips, but more complexity as well.

Currently, I'm reluctant to start playing with the DCSM until I fully understand this as it appears there are a number of pitfalls that could render the memories permanently locked. Any help or direction to a more detailed documentation would be appreciated. Do any of the training videos talk about the DCSM on one of the chips?

Thanks for any help,

-Wes

  • 0
    TI__Guru** 115881 points

    Hi Wesley,

    Why does each block in the Bank0 and Bank1 Zone have an associated register allocation for GRABSECT and GRABRAM?

    We have two zones. User can allocate different flash sectors and RAM blocks to different zone based on their need and that is done by programming GRABSECT and GRABRAM location in USER OTP. USER OTP location is secure hence user can not read it. For this reason OTP values get populated into GRABSECT and GRABRAM registers (READ ONLY).

    Further, why does the DSCM have multiple blocks per zone? Is this so that you can configure certain memories for special purposes (execonly, etc)?

    Same as explained in earlier point. If user wants to use only one zone then everything can be allocated to Zone1.

    Can I use just a few blocks or are they tied to specific purposes?

    You can use as many blocks you need.

    My previous experience with the CSM with an older Delfino was that setting the CSM registers would lock all the secure memories. It appears that there is a lot more flexibility in the CSMs of recent chips, but more complexity as well.

    You are right. We have added dual zone capability to allow third party development without compromising on security. But is that is not needed then it can be configured like old security scheme.

    We do not have video but there is example code in C2000Ware for F28377S device which can be referred or let me know the specific query and we would like to explain it further.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Intellectual 925 points

    Thank you for the reply Vivek,

    I think that my confusion was mostly due to going through the documentation and not looking at a sample project.

    Given your reply and looking at the registers via a sample project, I see 6 sets of registers:

    DcsmCommonRegs - This appears to be registers related to status and semaphores for all DCSM

    DcsmCommon2Regs - This appears to be empty. I suspect that in other chips this is populated for a common register structure?

    DcsmBank0Z1Regs - This appears to be Zone 1 Registers for Flash Bank 0 and RAMs

    DcsmBank0Z2Regs - This appears to be Zone 2 Registers for Flash Bank 0 and RAMs

    DcsmBank1Z1Regs - This appears to be Zone 1 Registers for Flash Bank 1

    DcsmBank1Z2Regs - This appears to be Zone 2 Registers for Flash Bank 1

    So  if I set the bits in DcsmBank0Z1Regs.B0_Z1_GRABSECTR_1, DcsmBank0Z1Regs.Z1_GRABRAMR_1, and DcsmBank1Z1Regs.B1_Z1_GRABSECTR_1, then I can allocate all the secure memory to Z1, right?

    Defaults appear to be:

    DcsmBank0Z1Regs.B0_Z1_GRABSECTR_1 = 0xFFFFFFFF

    DcsmBank1Z1Regs.B1_Z1_GRABSECTR_1 = 0xFFFFFFFF

    DcsmBank0Z1Regs.Z1_GRABRAMR_1 = 0x0000FFFF

    Going by documentation, if I set to 0x55555555 for the GRABSECTRs and 0x00005555 for the GRABRAMR, this should allocate everything to Zone 1, right?

    Thanks,

    -Wes

  • 0 in reply to Wesley C
    TI__Guru** 115881 points

    Hi Wes,

    So  if I set the bits in DcsmBank0Z1Regs.B0_Z1_GRABSECTR_1, DcsmBank0Z1Regs.Z1_GRABRAMR_1, and DcsmBank1Z1Regs.B1_Z1_GRABSECTR_1, then I can allocate all the secure memory to Z1, right?

    Please note that registers are read only. Actual value is programmed in USER OTP location for this.

    Going by documentation, if I set to 0x55555555 for the GRABSECTRs and 0x00005555 for the GRABRAMR, this should allocate everything to Zone 1, right?

    Correct but again, these values need to be programmed in USER OTP. This can be done by CCS flash plug-in GUI or including this into your code such that .out has all the required settings and get programmed when loading the .out.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Intellectual 925 points

    Vivek Singh said:

    including this into your code such that .out has all the required settings and get programmed when loading the .out.

    Hi Vivek,

    Regarding saving these to USER OTP, my team wants to do this programmatically as you indicated.I found the 'blinky_with_dcsm_cpu01' project in C200Ware for the 2837x series of processors. Once I can go through this I may have further questions, but I think that I'm good for now.

    Thanks!

    -Wes