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TMS320F28377S: For higher baud rates, SCI RX buffer is getting corrupted.

Part Number: TMS320F28377S


I am working with a code in which serial packets are receiving and transmitting. For reception there are time outs between each bytes for multi byte reception. So i need to enable and disable timer interrupts after each byte of reception. I have enabled a non fifo based reception with RX_RDY break detect interrupt. For a configuration of 8 data bit , none parity and stop bit 2, with baudrates less than 115200, i am able to receive each bytes successfully from SCIRXBUF register after each interrupt. But for baud rate 115200, it seems the bytes are getting corrupted after the reception of fist byte (which is correct) even if the interrupts are triggering correctly. For other configurations like stop bit = 1 or parity = odd/ even same issue is happening for all the baud rates and when i checked the flag register, it is seen that the Frame error bit is set. For transmission no error is happening and bytes are sending successfully. It seems the configuration is correct. What could be the issue ?  I am using LAUNCHXL-F28377S development kit with 3.3 V FTDI cable . Port used is SCI base C with GPIOs 89(tx) and GPIO 90( rx).

On further check it is seen that the stop bit for reception is only detecting if the number of stop bits are equal to 2 even though the controller is configured for stop bit = 1 (in transmission  stop bit  1 is correctly sending)

  • Hi Chrisjs,

    If it is failing as you crank up the baud rate, this would usually indicate that the baud rate timing tolerance is maybe being violated.

    What clock source are you using? The 10MHz XTAL on the board, the INTOSC, or something else? Have you measured XCLKOUT to determine the overall system SYSCLK accuracy (should be really good with external XTAL, but there will probably be some noticeable drift when using INTOSC).

    How accurate are the bit timings if you use an oscilloscope to observe a transmission (of e.g. 0x55)? How about for the timings of the incoming frame to be received?

    What is the actual baud based on your BRR setting vs the ideal 115200 baud? (see e2e.ti.com/.../761126)

    Alternately, is it possible that the ISR is taking too long to read the data? You could make the issue 'worse' intentionally by adding NOPs or delays at the beginning of the ISR and then seeing if the issue begins to manifest at lower baud rates. I don't think this is the case though since you are getting a physical bus error, which seems more like a timing issue.
  • Thanks Devin,

    I am using launchpad and configured 10MHz XTAL as clock source and believes it is working fine as it is working for other bauds (i am getting around 8.68us for 115200 for a bit in transmission). I have not measured the XCLKOUT as i dont have 200MHz oscilloscope. I have checked incoming and out going frames in oscilloscope and the timing seems ok. As i mentioned, i have to enable and disable timer interrupt between each byte reception (inside reception ISR)could have been making issues for the baud 115200. As you mentioned, the serial byte reception ISR will have some NOP when enabling and disabling the timer interrupts (As per the user manual for enabling and disabling interrupt, we need to disable global interrupts and wait for 5 cpu cycle for consuming any out standing interrupts).

    Is there a way to disable timer or any other peripheral interrupts with out disabling and enabling the global interrupt (and avoid NOPs too for consuming pending interrupts), which may affect other interrupts ?

    For baud 115200 the BRR value calculated is 53. (the link mentioned is not available and can you please share the same )

    The other issue mentioned was frame error when stop bit is set to one and happens after 1st byte successful reception. It only detects stop bit if it is 2 for reception. The transmission and reception timings seems ok as per oscilloscope. What could be the issue ? I have checked the related configurations and seems correct.

  • Hi Chrisjs,

    Sorry, looks like the link got an extra ')' on the end, which broke it. Try this:
    e2e.ti.com/.../761126

    BRR 53 with LSPCLK of 50MHz should give you within 0.5% of 115200. If you are using the X1 XTAL and have measured the bit timings I think we can conclude that a baud rate mismatch is probably not the issue.

    It should definitely be possible to disable the timer, not the timer interrupts. e.g. if you are using an ePWM you can set the count mode from up-count (or any other counting mode) to 'frozen' and then also reset the timebase counter. When you are ready to start counting again you can then resume a counting mode (e.g. up-count).

    I'm at a loss to explain the stop bit issue. The only other reference to a similar issue I could find on the e2e was caused by accidentally setting the baud rate to 2x the intended value due to LSPCLK being different than expected. What is the source of the incoming messages? Are they from a PC or some other device? If you loop the C28x sent messages back to the C28x, does it RX correctly?
  • Thanks Devin,

    The source of incoming message is PC.

    I have tried with an alternative . Instead of using SCIRXBUF upon RXRDY_BRKDT interrupt, tried RX FIFO interrupt with rx fifo interrupt level 1 (transmission is with out fifo and still using TX READY interrupt). It seems the new method is working.

    Now i have a thought like, why SCIRXBUF & RXRDY_BRKDT combination was not working? Would n't it be a problem if SCIRXBUF is accessing frequently with ISR ?

    I have not seen any code example, which is using SCIRXBUF & RXRDY_BRKDT interrupt. Is it possible to share a sample one?
  • Hi Chris,

    The only thing approaching an example for RX in non-FIFO mode is the following function in the driverlib:

    //*****************************************************************************
    //
    //! Determines if there are any characters in the receive buffer when the
    //! FIFO enhancement is not enabled.
    //!
    //! \param base is the base address of the SCI port.
    //!
    //! This function returns a flag indicating whether or not there is data
    //! available in the receive buffer.
    //!
    //! \return Returns \b true if there is data in the receive buffer or \b false
    //! if there is no data in the receive buffer.
    //
    //*****************************************************************************
    static inline bool
    SCI_isDataAvailableNonFIFO(uint32_t base)
    {
        //
        // Check the arguments.
        //
        ASSERT(SCI_isBaseValid(base));
    
        //
        // Return the availability of characters with FIFO disabled.
        //
        return(((HWREGH(base + SCI_O_RXST) & SCI_RXST_RXRDY) ==
                SCI_RXST_RXRDY) ? true : false);
    }

    Which is basically just returning RXST.RXRDY.

    I guess what should be done in non-fifo RX ISR is to check this flag at the beginning to determine if the ISR was caused by RXRDY or a break detect.  If caused by break detect, instead of reading data you should issue a module SW reset.  I don't think that helps you other than potentially explaining why the data is corrupt.  

    I'll submit for a non-fifo RX example to be written.  This will probably take awhile to get written and released.