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TMS320F280049: HRPWM and DMA

Part Number: TMS320F280049
Other Parts Discussed in Thread: C2000WARE

Hello,

My customer needs to generate a signal in the order of 100 kHz using ePWM or HRPWM. The choice between both is pending the THD assessment, but likely it will be the HRPWM since (after the table 19-1 in the TRM) the ePWM would give a 10-bit resolution at this frequency which is a bit low. The signal period is a multiple of the CPU core frequency. He pre-computes a table of values that will be transferred by DMA to the ePWM/HRPWM.

Questions:

  • Assuming he uses the ePWM, is "C2000Ware_1_00_06_00\device_support\f2833x\examples\epwm_dma" the closest example to the above?
  • Do we have any HRPWM example he could leverage?
  • The ePWM and HRPWM duty cycle will be changed for each PWM period. What is the highest update rate at which the duty cycle register may be updated? The current thought is to have a 4 MHz PWM period, but would 8 or 16 work as well?


Thank you.

Best regards,
François.

  • H Francois,

    Any reason not to use the buffered DAC module? This should be able to generate a signal at 100kHz and it has 12-bit resolution and is DMA mapped.

    HRPWM is not DMA mapped (and is CPU1 only) so I think to get a really high update rate like you are requesting you will have to use a significant portion of CPU1 bandwidth.
  • Hi Devin,

    Thank you. I had missed this fact. We had initially chosen to generate the signal with the PWM because we were hoping to migrate to a device that does not integrate DACs. So we will stick to the F28004x.

    Best regards,
    François.
  • Hi Devin,

    I have reopened this thread because Table 6-9 of the F28004x datasheet does say the DMA has access to the ePWM/HRPWM. Could you please comment on any limitation there would be in controlling the HRPWM duty cycle using the DMA?

    Thanks,
    François.
  • Hi Francois,

    Sorry for the delay.

    You should be able to use the DMA to control the HRPWM duty cycle.  The limitation of HRPWM control via DMA is that EALLOW protected registers can't be written by the DMA.  For simple direct duty cycle control using e.g. CMPAHR you should be fine.

    As far as maximum ePWM speed, you may want to consider the minimum HRPWM duty-cycle limitation (see below).

    Each time the frequency doubles, so does the minimum duty cycle, so

    • 4MHz: the minimum duty is 12%
    • 8MHz: the minimum duty is 24%
    • 16MHz the minimum duty is 48%

  • Hi,

    I am trying to build an example but I encounter difficulties to trig the DMA by ePWM SOCA.
    I am new in the DMA world.
    Why should the DMA be triggered (by a timer or other trigger source) ? At which frequency has ?
    So due to the timer limitation, could the DMA be triggered at 4MHz (or higher) frequency by a ePWM ?
    Could the DMA be triggered only one time per period of 10us ? Maybe with One Shot Mode ?
    Why should it be triggered at the sampling frequency ? Is it to trigger the DMA state machin ?
    If Data Size Mode is set to 32-bit transfer I understand that the DMA could be triggered at the half of sampling frequency.

    Thanks for your response
    Regards
    Yann
  • Hi Yann,

    I think you want to trigger a transfer of a single value (one new CMP value) each ePWM period.

    You could also potentially transfer words less frequently (e.g. every-other period).

    I don't think you need to set one-shot mode or continuous mode. I think a normal single-value transfer is fine. As best I can tell, you'd want something along the lines of:
    -source transfer step = 1 (to walk through values in the waveform table)
    -destination transfer step = 0 (because you always want to write to the same CMP location)
    -wrap step = size of waveform table (to wrap back to the beginning of the table after stepping through the full table)
  • Hi
    Due to limitations on PWM at a frequency over 4MHz we have dropped this solution to generate a signal of 100 kHz
    Regards
    Yann