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TMS320F28374S: Vref 3.3V

Anders Lange
Genius 14355 points
Part Number: TMS320F28374S


The ADC Signal References are listed in Table 5-44 ADC Operating Conditions (12-Bit Single-Ended Mode)] of the datasheet as having a nominal maximum voltage of 3.3V. With a nominal typical value of 2.5V to 3.0V.

Further table 5-45 [ADC Characteristics (12-Bit Single-Ended Mode)] specifies various error, noise, and performance characteristics of the ADC. Specifically these characteristics are given at 2.5V VREF.

Has TI quantified the characteristics of the ADC at a VREF of 3.3 or even 3.0V?

What is the benefit (if any) of running VREF at 2.5V instead of 3.0V? (From the perspective of the tms320f28374s Performance.)

Is there any danger in running VREF at 3.3V?

BR

Anders Lange

  • 0
    TI__Guru 60865 points
    Hi Anders,

    The internal ADC noise sources mostly have a constant absolute magnitude, so characterizing with the minimum VREFHI gives the worst-case performance. I believe you can e.g. expect typical SNR to increase by up to 20*log(3.0/2.5) = 1.6dB by using VREFHI = 3.0V.

    The maximum VREFHI value is VDDA. The VREFHI < VDDA is a strict requirement for correct operation, so using VREFHI = 3.3V would require something like setting the typical VDDA voltage to 3.3V + 2.5% with a tolerance of +/- 2%.
    Using a lower VREFHI like 2.5V does have the advantage of allowing the signal conditioning circuits to be powered by VDDA with ample head-room, making power-sequencing and input protection from over-voltage simple and automatic.