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Tool/software: Code Composer Studio
Hello!
I connected the library "C28x Floating Point Unit fastRTS Library" to my project. But the implementation of division and square root operations take more cycles than stated in the library documentation. The library states that the division operation is performed in 24 cycles and the square root in 28 cycles. In my project, these operations require 29 clock cycles (division) and 33 clock cycles (square root).
Tell me what could be the problem?
Below is my code. Red lines, the execution time of which I checked. Also, just in case, I attach the archive with my project.
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#include "main.h"
#include <math.h>
uint16_t ADC_DATA_0[5] = {0, 0, 0, 0, 0};
float ADC_DATA_0_mean = 0;
float ADC_DATA_0_real = 0;
float ADC_DATA_0_reall = 0;
int i = 0;
float x1 = 0.5f;
float x2 = 0.9f;
float x3 = 0.0f;
float x4 = 5.2f;
void adcA1ISR(void);
void main(void)
{
InitStartMCU();
InitPWM();
InitADC();
InitADCSOC();
EALLOW;
PieVectTable.ADCA1_INT = &adcA1ISR; // Function for ADCA interrupt 1
EDIS;
IER |= M_INT1; // Enable group 1 interrupts
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
// Enable PIE interrupt
//
PieCtrlRegs.PIEIER1.bit.INTx1 = 1;
/*********************************************************************************************************************************************/
EALLOW;
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 0; // GPIO2 = GPIO2
GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1; // Disable pullup on GPIO2
GpioCtrlRegs.GPADIR.bit.GPIO2 = 1; // Load output latch
EDIS;
/**********************************************************************************************************************************************/
while(1)
{
}
}
__interrupt void adcA1ISR(void)
{
if (i>=4) {
i = 0;
}
else {
i++;
}
ADC_DATA_0[i] = AdcaResultRegs.ADCRESULT0;
ADC_DATA_0_mean = ( ADC_DATA_0[0] + ADC_DATA_0[1] + ADC_DATA_0[2] + ADC_DATA_0[3] + ADC_DATA_0[4] ) / 5;
ADC_DATA_0_reall = ADC_DATA_0_mean * 3.3;
ADC_DATA_0_real = ADC_DATA_0_reall / 4096;
GpioDataRegs.GPASET.bit.GPIO2 = 1;
x3 = x2 / x1;
x3 = sqrt (x1);
GpioDataRegs.GPACLEAR.bit.GPIO2 = 1;
x3 = x2 * x4 + x1;
//
// Clear the interrupt flag and issue ACK
//
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}
Hi Andrey,
The actual computation of division and square root using FPU FastRTS takes 24 and 28 cycles respectively. But as these routines are not intrinsic rather it involves a function call to these assembly routines of the library. I guess thats why there is an overhead of 5 cycles just in case of normal function call.
Regards
Himanshu