Hello,
I am using the TMS320F28379D for a new project and I'm wondering about the best way to use both cores and I'm not sure how to proceed.
I have two kinds of computations that need to be done:
- Supervision/Communications
- Control
Usually (with Piccolo devices) I would use the CPU for Supervision/Communications and the CLA for Control. However I have too many control loops so CLA1 will not be enough to perform all computations. Therefore I wish to use CLA2.
At first I wanted to use CLA2 for the control loops which manage some of the ePWM modules, but in this project only ePWMs with HRPWM are being used. Only core 1 can use HRPWM so CLA2 cannot update the ePWM+HRPWM registers on its own.
- There is no shared memory between CLA2 and CLA1 so I cannot simply compute the register values with CLA2 and let CLA1 read them to perform the actual write operations to the registers.
- There is no shared memory between CLA2 and DMA2 so I cannot use DMA2 to transfer the computation results from CLA2 to CPU1.
Thus CPU2 must be used to perform the transfers. I had already planned to use it for something else but so be it. For instance I can make room for a small interrupt after each CLA2 task to copy the results from LSRAM to GSRAM.
Now I need to transfer the results from GSRAM to CLA1 so that it can use them to update the ePWM+HRPWM registers.
- There is no shared memory between CLA1 and DMA1 so I cannot use DMA1 to transfer the results from GSRAM to CLA1.
- I'm not certain that DMA1 can write to ePWM+HRPWM registers but even if it could it would not be enough because SECMSEL_1[PF1SEL] apparently makes it impossible that some ePWM modules have their registers written by CLA1 while others have their registers written by DMA1.
So CPU1 must be used to perform additional transfers. CPU1 is already quite busy but the minimum it has to do will be to transfer the values from GSRAM to LSRAM and let CLA1 perform the actual ePWM+HRPWM register writes. These transfers must be performed in a timely manner, otherwise the stability of the control loop will be degraded. Therefore I must make room multiple interrupts on CPU1.
Now the problem is that the SFO() function with its uninterruptible RPT instructions must be called from time to time, and it can delay my interrupts on CPU1. The sampling frequency and modulation scheme are such that I cannot afford to let more than 300ns elapse between a new ADC sample becoming available and a the new register values being written to the corresponding ePWM module.
Is there any way to meet all these requirements?
Obviously it would be much simpler if CLA1 and CLA2 had any way to share data directly, or if the HRPWM could be used from core #2. Without these options, having a dual-core DSP becomes less useful than it first seemed.
Thanks in advance,
Pierre
