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SM320F28335-HT: XCLKIN duty cycle

John Smith
Intellectual 410 points

Part Number: SM320F28335-HT
Other Parts Discussed in Thread: TMS320F2808

Hi There

I'm using the SM320F28335-HT for a high temperature application. I'm currently specifying an external 3.3V crystal oscillator, most high temperature crystal oscillators seem to have a duty cycle of 40/60. Table 6-6 of the data sheet seems indicate 45/55 is required.

1) Can you confirm a clk input of 45/55 duty cycle is required?

2) what happens if i break this rule?

3) how is the duty cycle calculated? (ie is it function of the clock frequency and rise/fall times?

4) If it is, can i reduce the 45/55 requirement with a slower clock?

Kind Regards

Martin

  • 0
    Prodigy 180 points
    By coincidence, I'm scouting around for the same info, for the TMS320F2808, so will keep an eye on this thread.

    I observe that the industry norm is to specify Duty Cycle with 5% granularity, so presumably 45/55 has been specified for the 320F28 because it couldn't manage at 40/60 across the entire range of PVT (Process/Voltage/Temperature). Likewise, your high temperature oscillators are possibly 40/60 only because they cannot hold to 45/55 for the entire PVT range. A finer granularity could be helpful for all clock chain designers. In some cases, clock buffer designers do specify a Duty Cycle with a tighter tolerance for lower frequency clocks for a single part.

    Along the same lines as question 2) above, is it possible to say where a marginal duty cycle first reveals behavioural problems for the 320F28?

    You might find that another option for your high temperature situation is to choose higher frequency oscillator and divide by 2 using a D-type. That way, the D-type generates more reliable duty cycle because it is triggering from the same oscillator clock edge.

    Best Regards

    Andy.
  • 0 in reply to Andrew Jones94
    Intellectual 410 points

    Hi Andy

    thanks for comments

    i spent a few hours yesterday trying to research the "need" for 45/55 oscillators and couldn't get a straightforward answer. i suspect its due to the minimum pulse width needed by processor to detect a clock signal and thus at lower frequencies you can get away with more. but it would be great if somebody at TI could confirm?

    Many thanks for your D-type suggestion, i keep that in my back pocket if all else fails (i'm tight on real estate so will like to avoid if possible)

    Kind Regards

    Martin

  • 0 in reply to John Smith
    TI__Guru 62930 points

    Martin,

    I do not have any specific data that indicates that you can violate the 45/55 duty cycle if you relax the clock frequency.

    I believe the tighter constraints for duty cycle are primarily related to the PLL block, and its correct functionality.  It very likely is using both edges of the clock to multiply the input clock.  Slowing input clock might improve the worst case duty cycle for proper operation.  However, this is not a tested nor characterized condition.  Some of the peripherals may also be using the negative edge of the clock.

    You can also bypass the PLL and provide a slower clock with 40/60 dutycycle.   While this also is not tested nor characterized, it should give you better chances of proper device operation.

    If this answers your question, please click "Verify it as the answer"
    Regards,
    Wade