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CCS/TMS320F28379D: DMA missing every other trigger from ePWM

Ron Krahe
Prodigy 70 points

Part Number: TMS320F28379D

Tool/software: Code Composer Studio

I'm trying to setup a DMA transfer of four 32-bit words, one word per burst, from RAMGS0 table to ePWM1 CMPA all.

 #define NN 4

 Uint32 ATable[NN]={327680L,655360L,983040L,655360L};  // mid wide mid narrow

But the HRPWM output repeats each one like 327680L,327680L, 655360L,655360L, 983040L,983040L, 655360L,655360L.

So I get 8 :   // mid mid wide wide mid mid narrow narrow

instead of 4 like I want.

void HRPWM_Config(PwmRegs *regs, int period) {
   (*regs).TBPRD = period; // PWM frequency = 1 / period
   (*regs).ETSEL.bit.SOCASEL=1; // 
   (*regs).ETPS.bit.SOCAPRD=1; // on first event
   (*regs).ETSEL.bit.SOCAEN=1; // enable
   (*regs).ETSEL.bit.SOCBSEL=1; // 
   (*regs).ETPS.bit.SOCBPRD=1; // on first event
   (*regs).ETSEL.bit.SOCBEN=1; // enable
   (*regs).TBCTL.bit.CTRMODE = TB_COUNT_UP;
   (*regs).TBCTL.bit.HSPCLKDIV = TB_DIV1;
   (*regs).TBCTL.bit.CLKDIV = TB_DIV1;
   (*regs).TBCTL.bit.FREE_SOFT = 11;
   (*regs).CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; //
   (*regs).CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   (*regs).CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; //
   (*regs).CMPCTL.bit.SHDWBMODE = CC_SHADOW;
   (*regs).AQCTLB.bit.ZRO = AQ_SET; // go hi at zero,
   (*regs).AQCTLB.bit.CAU = AQ_CLEAR; // go lo at CMPA
   (*regs).AQCTLA.bit.ZRO = AQ_SET;
   (*regs).AQCTLA.bit.CAU = AQ_CLEAR;
   (*regs).HRCNFG.all = 0x0;
   (*regs).HRCNFG.bit.EDGMODE = HR_FEP; 
   (*regs).HRCNFG.bit.CTLMODE = HR_CMP;
   (*regs).HRCNFG.bit.HRLOAD = HR_CTR_ZERO;
   (*regs).HRCNFG.bit.EDGMODEB = HR_REP; 
   (*regs).HRCNFG.bit.CTLMODEB = HR_CMP;
   (*regs).HRCNFG.bit.HRLOADB = HR_CTR_ZERO;
   (*regs).HRCNFG.bit.AUTOCONV = 0;
   (*regs).HRPCTL.bit.HRPE=0;
   (*regs).TBCTL.bit.SWFSYNC=1;
}

void dma_init() {
   EALLOW;
   PieVectTable.DMA_CH4_INT= &local_D_INTCH4_ISR;
   EDIS;
   DMAInitialize();
   DMACH4AddrConfig32bit(&EPwm1Regs.CMPA.all,ATable);
   DMACH4BurstConfig(1,0,0); // burst size, src step, dest step
   DMACH4TransferConfig((2*NN-1),1,0); // transfer size, src step, dest step
   DMACH4WrapConfig(0xFFFF,0,0xFFFF,0); // src size, step, dest size, step
   DMACH4ModeConfig(DMA_EPWM1A,PERINT_ENABLE,ONESHOT_DISABLE,CONT_ENABLE,
   SYNC_ENABLE,SYNC_SRC,OVRFLOW_DISABLE,THIRTYTWO_BIT,
   CHINT_BEGIN,CHINT_ENABLE);
   EALLOW;
   CpuSysRegs.SECMSEL.bit.PF1SEL = 1;
   EDIS;
}

  • 0
    TI__Guru 55700 points

    Ron,

    If you want to transfer just 1 word / burst you need to set BURST_SIZE as 0. Also, shouldn't your TRANSFER_SIZE be 3 instead of 7.

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    Prodigy 70 points

    Thanks, Manoj. But the note on page 637 says the burst size and transfer size are in 16-bit words, so I want to burst one 32-bit word, so that is two 16-bit words, so I set burst size = 1. And I want to transfer four 32-bit words, so that is eight 16-bit words, so I set transfer size = 7. I tried your suggestion and it only sends two of the four values.

    "NOTE: Regardless of the state of the DATASIZE bit, the value specified in the SIZE registers are for 16-bit addresses. So, to transfer three 32-bit words, the value 5 should be placed in the SIZE register."

  • 0 in reply to Ron Krahe
    TI__Guru 55700 points
    Ron,

    In 32 bit mode, BURST_SIZE = 0 (or) 1 would transfer only one 32-bit word / Burst. TRANSFER_SIZE just tells the number of bursts per transfer and it is independent of 32 bit mode / 16-bit mode. So, if you have 4 bursts, then set TRANSFER_SIZE = 3.

    We have some changes to DMA chapter in TRM where we have addressed some of these issues better. This is currently not available to customers but should be available in next month (or) so.

    Regards,
    Manoj
  • 0 in reply to Manoj Santha Mohan
    Prodigy 70 points

    Thank you, again, Manoj, but that does not work.

    The HRPWM  now puts out two narrow pulses and two mid pulses:  327680L,  327680L,     655360L,  655360L

    instead of one each narrow, mid, wide, mid that I want:  327680L,  655360L,  983040L,  655360L.

    The DMA is now only sending 2 bursts. And the HRPWM is putting out four pulses (two each of the first two values).

       DMAInitialize();

       DMACH4AddrConfig32bit(&EPwm1Regs.CMPA.all,ATable);

       DMACH4BurstConfig(0,0,0); // burst size, src step, dest step

       DMACH4TransferConfig(3,1,0); // transfer size, src step, dest step

       DMACH4WrapConfig(0xFFFF,0,0xFFFF,0); // src size, step, dest size, step

       DMACH4ModeConfig(DMA_EPWM1A,PERINT_ENABLE,ONESHOT_DISABLE,CONT_ENABLE,

                        SYNC_ENABLE,SYNC_SRC,OVRFLOW_DISABLE,THIRTYTWO_BIT,

                        CHINT_BEGIN,CHINT_ENABLE);

  • 0 in reply to Ron Krahe
    TI__Guru 55700 points
    Ron,

    Please check the configuration of HRPWM as EPWM1A is the trigger source. Unless there is a trigger there won't be DMA burst.

    Were you able to confirm EPwm1Regs.CMPA.all gets modified with 327680L and 655360L?

    Regards,
    Manoj
  • 0 in reply to Manoj Santha Mohan
    Prodigy 70 points

    Manoj, yes EPWM1A is the DMA trigger (see the source code I included with my original post).

       DMACH4BurstConfig(0,0,0); // burst size, src step, dest step
       DMACH4TransferConfig(3,1,0); // transfer size, src step, dest step

       DMACH4ModeConfig(DMA_EPWM1A,PERINT_ENABLE,ONESHOT_DISABLE,CONT_ENABLE,
       SYNC_ENABLE,SYNC_SRC,OVRFLOW_DISABLE,THIRTYTWO_BIT,
       CHINT_BEGIN,CHINT_ENABLE);

    See attached media file PWM.BMP. The Violet trace is a GPIO pin toggled in the DMA ISR, and the Yellow trace is the output of the PWM. Notice that there are two narrow pulses and two midsize pulses. There should be a narrow, midsize, wide, and midsize per the data in the DMA array (four 32-bit values).

  • 0 in reply to Ron Krahe
    Prodigy 70 points

    FYI. This is what ended up working to transfer NN 32-bit words, bursting one 32-bit word at a time.

       DMACH4BurstConfig(2,1,0); // burst size, src step, dest step

       DMACH4TransferConfig(NN-1,1,0); //transfer size, src step, dest step