CCS: TIDM_HV_1PH_DC_AC SFRA question

Michael Koval27

Other Parts Discussed in Thread: SFRA, TIDM-HV-1PH-DCAC

Tool/software: Code Composer Studio

Hello! We try to use SFRA in project like TIDM_HV_1PH_DC_AC. There is order of using of SFRA in project described as : first open loop Current, then close Current loop and next is implemented SFRA for Voltage. I wonder is there sense in such an order? Is it possible first to use SFRA open loop for Voltage coefficients. And next for current coefficients. Or it depends from where we want to apply our device. For us it is important strict control of Voltage out and current only for not to overload device. Please explain what is the difference in order of using of SFRA Current/ Voltage. Or may be the order is not important and result should be independent of order.

over 7 years ago

0 Manish Bhardwaj over 7 years ago

TI__Mastermind 43730 points

HI Michael.

There are two fundamental questions

1. Why use casaded control for VSI,

The inner current loop in the VSI design makes the control of the voltage loop easier as it is less dependent on the load.

You can try different methods, we do not restrict as everything is avaialble as source.But at that point this discussion is academic and something we do not support through the forums.

www.ti.com/.../tiduay6c.pdf

you can check related documents, section 10

reference 1, and 2 for discussion on control architectures.

3. SFRA usage in open loop

Now, about running SFRA in open loop. Please note SFRA is based on small signal injection and if the plant gain is very higfh in open loop the SFRA injection can lead to large disturbance on the output which can violate the conditions for small signal injection to be valid. Hence on this design we document only the running of SFRA in closed loop. We have the model in compensation designer and you can use that as the first pass coefficients.

-Manish

0 Michael Koval27 over 7 years ago in reply to Manish Bhardwaj

Intellectual 990 points

Thank you. But in app_libs/SFRA project for SFRA. Build-1 is used to get coefficients for open_loop:
DPSWrkShpKit_SFRA-Main.c :

interrupt void PWM_ISR(void)
{
//TODO PWM ISR

#if (INCR_BUILD==1)
//Read ADC and computer Fbk Value
Vout1_Read= _IQsat((((int32)Vout1R<<12)-offset_Vout),_IQ24(1.0),_IQ24(0.0)); //(int32)Vout1R<<12;

//Add SFRA injection into the duty cycle for the open loop converter
Duty_pu=SFRA_IQ_INJECT(Duty_pu_DC);

//Update PWM value
EPwm1Regs.CMPA.half.CMPA=_IQ24mpy((long)(BUCK_PWM_PERIOD),Duty_pu);

SFRA_IQ_COLLECT(&Duty_pu,&Vout1_Read);
#endif

#if (INCR_BUILD==2)

//Read ADC and computer Fbk Value
cntl3p3z_vars1.Fdbk= _IQsat((((int32)Vout1R<<12)-offset_Vout),_IQ24(1.0),_IQ24(0.0));

//Add SFRA injection into the reference of the controller
cntl3p3z_vars1.Ref= SFRA_IQ_INJECT(Vout1SetSlewed);

// Call the controller
CNTL_3P3Z_IQ_ASM(&cntl3p3z_coeff1,&cntl3p3z_vars1);

//Update PWM value
EPwm1Regs.CMPA.half.CMPA=_IQ24mpy((long)(BUCK_PWM_PERIOD),cntl3p3z_vars1.Out);

SFRA_IQ_COLLECT(&cntl3p3z_vars1.Out,&cntl3p3z_vars1.Fdbk);

#endif

0 Manish Bhardwaj over 7 years ago in reply to Michael Koval27

TI__Mastermind 43730 points

Michael,

Sure, I am not denying that it cannot be done, I was trying to explain to you it's usage and determinism of the data will depend on the topology , what gain it has etc. And this was the reason we chose not to document it that way for the TIDM-HV-1PH-DCAC. Also please note there are lots of permutations and combinations possible , we may not be able to document all the methods possible. We document one which we used. And in that case because we had the model, we did not need to measure in open loop.

If you feel that you need to do open loop plant measurement, that is perfectly supported with SFRA.

-Manish

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CCS: TIDM_HV_1PH_DC_AC SFRA question