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TMS320F28377D: DMA CPU Arbitration

Part Number: TMS320F28377D

Hi,

in spruhm8g.pdf, Section 4.4 of the TRM, it indicates that "In the case of a bulk DMA transfer to and from the same memory block the CPU is trying to access,

the arbitration will stall CPU access until the DMAcompletes single access, not the entire bulk transfer".

Now, I have a case,

DMA CH1/CH2/CH4 cpu1 cpu2 , they use the same EMIF,

DMA CH4 wants to transfer 160 words memory block,

Setting DMA BURST_SIZE=2, & TRANSFER_SIZE=80,

DMA CH1/CH2 cpu1 cpu2,   they can not use EMIF when DMA CH4 working.

Is the above description right?

best regards,

Simen

  • Hi Simen,

    DMA does read and write from same interface hence after every write access to EMIF there will be cycle where CPUx can get access to EMIF when DMA is reading next data from internal memory. ON DMA channel it's different. Since DMA has only one physical channel (6 logical channels) other channels can not get access unless current channel is done.

    Regards,

    Vivek Singh

  • Simen,

    I believe CH1 / CH2 / CH4 are configured to access EMIF peripheral. Am I correct?

    Assuming I got your question right. Here is the expected behavior

    When Oneshot mode is not invoked:
    Neither CH1 (or) CH2 have access to EMIF until CH4 burst is complete (which in your case is until CH4 completes transferring 3 words). Once completed CH1 (or) CH2 can have access to EMIF depending upon which channel gets triggered and channel priority.

    When Oneshot mode is invoked:
    Neither CH1 (or) CH2 have access to EMIF until CH4 all bursts is complete (which in your case is until CH4 completes transferring 3 x 81 = 243 words). Once completed CH1 (or) CH2 can have access to EMIF depending upon which channel gets triggered and channel priority.

    If you're trying to transfer 160 words with 2 words/ burst and 80 bursts. You need to configure the BURST_SIZE and TRANSFER_SIZE as follows:

    BURST_SIZE = 1 ( does 2 words / burst)
    TRANSFER_SIZE = 79 (does 80 bursts in total)

    Regards,
    Manoj
  • Monoj,

    Yes ,DMA CH1 / CH2 / CH4 are configured to access EMIF peripheral.
    CPU1 and CPU2 also access EMIF peripheral.

    I made a summary with yours and vivek's opinions:
    1. DMA just has one physical channel, it cannot use more than 2 channels at the same time.
    2. When transfer 160 words , the setting is BURST_SIZE = 1 &TRANSFER_SIZE = 79 .
    3. DMA Oneshot mode is not invoked, DMA CH4 can be interrupted by ch1/ch2 during ch4 transferring 160 words.
    There is a time interval between 1st burst and 2nd burst of data transfer.
    4. DMA Oneshot mode is invoked, DMA CH4 can not be interrupted by any channel during ch4 transferring 160 words.
    5. Every time DMA access have a time interval .
    During ch4 transferring 160 words, CPUx always can access EMIF from DMA access time interval ,no matter what DMA setting .
    (Due to"DMA does read and write from same interface hence after every write access to EMIF there will be cycle where CPUx can get access to EMIF when DMA is reading next data from internal memory." )

    Is there any mistake in my concepts?
    The 5th item, CPUx access EMIF frequcency depending burst size ? or each word transferring ?

    best regards,
    Simen
  • Hi Simen,

    On the Ist item -

    1. DMA just has one physical channel, it cannot use more than 2 channels at the same time.

    It can not use more than 1 channel at same time (unless you are interpreting the channel differently).

    The 5th item, CPUx access EMIF frequcency depending burst size ? or each word transferring ?

    No, it does not depends on burst size because CPU get a slot after every single DMA access.

    Regards,

    Vivek Singh

  • Simen,

    I believe Vivek S has clarified your remaining questions as well. Can we close this thread?

    -Manoj
  • Manoj and Vivek,

    Thanks a lot for your detail answers.

    best regards,
    Simen