Compiler/TMS320F28379D: TMS320F28379D

Tool/software: TI C/C++ Compiler

Hi, 

The coder is not entering the ISR, What I am doing wrong ?

 Any suggestion?

#include "F28x_Project.h"

void InitEQep1Gpio(void);
void InitEQep1(void);
__interrupt void EQep1_isr(void);

int Count;
int Loop_count;

void main(void)
{
//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xD_SysCtrl.c file.
//

     InitSysCtrl();

//
// Step 2. Initialize GPIO:
// This example function is found in the F2837xD_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
//
    InitGpio(); // Skipped for this example

    CpuSysRegs.PCLKCR4.bit.EQEP1=1 ;

    InitEQep1Gpio();

    // Step 3. Clear all interrupts and initialize PIE vector table:
    // Disable CPU interrupts
    //
        DINT;

    //
    // Initialize the PIE control registers to their default state.
    // The default state is all PIE interrupts disabled and flags
    // are cleared.
    // This function is found in the F2837xD_PieCtrl.c file.
    //
        InitPieCtrl();

    //
    // Disable CPU interrupts and clear all CPU interrupt flags:
    //
        IER = 0x0000;
        IFR = 0x0000;

    //
    // Initialize the PIE vector table with pointers to the shell Interrupt
    // Service Routines (ISR).
    // This will populate the entire table, even if the interrupt
    // is not used in this example.  This is useful for debug purposes.
    // The shell ISR routines are found in F2837xD_DefaultIsr.c.
    // This function is found in F2837xD_PieVect.c.
    //
        InitPieVectTable();

    //
    // Map ISR functions
    // Step 4. Initialize the Device Peripherals:
    //
        EALLOW;
        PieVectTable.EQEP1_INT = &EQep1_isr;
        EDIS;

        EALLOW;
            CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =0;
            EDIS;

            InitEQep1();

            EALLOW;
            CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =1; //Serve per sincronizzare gli interrupt
            EDIS;
 // Step 5. User specific code, enable interrupts:
 // Initialize counters:
//
//
// Enable CPU INT3 which is connected to EPWM1-3 INT:
//

          IER |= M_INT5;
//
// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3
//

          PieCtrlRegs.PIEIER5.bit.INTx1 = 1;

          // Enable global Interrupts and higher priority real-time debug events:
          //
              EINT;  // Enable Global interrupt INTM
              ERTM;  // Enable Global real-time interrupt DBGM

          //
          // Enable XINT1 and XINT2 in the PIE: Group 1 interrupt 4 & 5
          // Enable INT1 which is connected to WAKEINT:
          //
              PieCtrlRegs.PIECTRL.bit.ENPIE = 1;          // Enable the PIE block

              IER |= M_INT1; //Enable group 1 interrupts
              EINT;

              for(;;)
              {
                  Loop_count++;
               }
          }


__interrupt void EQep1_isr(void)
{
    Count++;

    //
    // Clear INT flag for this timer
    //
    EQep1Regs.QCLR.bit.IEL = 1;

    //
    // Acknowledge this interrupt to receive more interrupts from group 3
    //
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
}

void InitEQep1Gpio(void)
{
    EALLOW;

    //
    // Disable internal pull-up for the selected output pins
    // for reduced power consumption
    // Pull-ups can be enabled or disabled by the user.

    GpioCtrlRegs.GPAPUD.bit.GPIO20 = 1;    // Disable pull-up on GPIO20 (EQEP1A)
    GpioCtrlRegs.GPAPUD.bit.GPIO21 = 1;    // Disable pull-up on GPIO21 (EQEP1B)
//    GpioCtrlRegs.GPAPUD.bit.GPIO22 = 1;    // Disable pull-up on GPIO22 (EQEP1S)
    GpioCtrlRegs.GPAPUD.bit.GPIO23 = 1;    // Disable pull-up on GPIO23 (EQEP1I)
    //
    // Synchronize inputs to SYSCLK
    // Synchronization can be enabled or disabled by the user.
    // Comment out other unwanted lines.
    //

    GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0;   // Sync GPIO20 to SYSCLK  (EQEP1A)
    GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0;   // Sync GPIO21 to SYSCLK  (EQEP1B)
//    GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0;   // Sync GPIO22 to SYSCLK  (EQEP1S)
    GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 0;   // Sync GPIO23 to SYSCLK  (EQEP1I)
    //
    // Configure EQEP-1 pins using GPIO regs
    // This specifies which of the possible GPIO pins will be EQEP1 functional
    // pins.

    GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1;    // Configure GPIO20 as EQEP1A
    GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1;    // Configure GPIO21 as EQEP1B
//    GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1;    // Configure GPIO22 as EQEP1S
    GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1;    // Configure GPIO23 as EQEP1I
    EDIS;
}

void InitEQep1()
{
    EQep1Regs.QUPRD = 2000000;            // Unit Timer for 100Hz at 200 MHz
                                          // SYSCLKOUT
    EQep1Regs.QDECCTL.bit.QSRC = 00;      // QEP quadrature count mode
    EQep1Regs.QEPCTL.bit.FREE_SOFT = 2;
    EQep1Regs.QEPCTL.bit.PCRM = 00;       // PCRM=00 mode - QPOSCNT reset on
                                          // index event
    EQep1Regs.QEPCTL.bit.UTE = 1;         // Unit Timeout Enable
    EQep1Regs.QEPCTL.bit.QCLM = 1;        // Latch on unit time out
    EQep1Regs.QPOSMAX = 0xffffffff;
    EQep1Regs.QEPCTL.bit.QPEN = 1;        // QEP enable
    EQep1Regs.QCAPCTL.bit.UPPS = 5;       // 1/32 for unit position
    EQep1Regs.QCAPCTL.bit.CCPS = 6;       // 1/64 for CAP clock
    EQep1Regs.QCAPCTL.bit.CEN = 1;        // QEP Capture Enable
    EQep1Regs.QEINT.bit.IEL = 1 ;
    EQep1Regs.QEPCTL.bit.IEL = 1;

}