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TMS320F28335: SCI catches framing-error very often when baud-rate differs a little

Baranov Mihail
Intellectual 350 points

Part Number: TMS320F28335

In short: two TMS320F28335 communicate with SCI via RS485 on 9600 Hz. If the dividers of SCI differs on one point, framing error start happening really frequently. Clock generators are the same. One point of the divider is only 12 Hz in my case. What might be the problem?

I've got two devices with TMS320F28335 communicating with each other via RS485. If I set the same baud-rate devider on SCI on both MCU, everything works fine. Another device connected to the same bus operating on the same baud-rate provokes framing-error on my receivers with TMS320F28335.

I discovered that if I increase baud-rate devider on one point from 482 to 483 (baud-rate is 9600, 37.125 MHz slow peripheral bus clock rate) on one of my devices, framing error happens much rare on the frames from the other devices. But framing errors start happening on another of devices with  TMS320F28335.

A osciloscope shows me not much differene between two close values of the divider.

Thank you in advance

  • 0
    TI__Genius 17315 points
    Baranov,

    From what you have described, the two TMS320F28335 SCI peripherals are communicating as expected. If the divider differs slightly you should expect to see the error since this small difference is cumulative over time. Obviously as you have found, to avoid the error the two SCIs need to be set the same.

    The issue that you are experiencing is when you are introducing 'another device'. This device, which could be from another manufacturer, would need to match the settings used with the F28335 SCI to work properly. Please check with data sheet for your other device to make sure that it matches the F28335 SCI settings.

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken
  • 0 in reply to Ken Schachter
    Intellectual 350 points
    " since this small difference is cumulative over time"

    Why is it so? I expect SCI to reset its bit-timing clock on every frame (every start bit) as usual with UART. Am I missing something?
  • 0 in reply to Baranov Mihail
    TI__Genius 17315 points

    Baranov,

    Sorry for the confusion. There will be some clock skew over time, but it does get corrected with a new frame. Could you please let me know if you are operating the F28335 at 150 MHz? If so, with the LSPCLK set at the default of divide by 4 the SCI clock will be 37.5 MHz. I noticed in your earlier post you have 37.125 MHz. Using 37.125 MHz and 482 does give a baud rate of 9608, however if using 37.5 MHz and 482 the baud rate would be 9705. Please double check this and make sure the 'other' device matches the settings used with the F28335.

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken

  • 0 in reply to Ken Schachter
    Intellectual 350 points
    Thank you for the reply!
    The clock generator on the input of F28335 is 27 MHz (I've just rechecked it by an osciloscope), PLLCR DIV is 11, PLLSTS DIVSEL is 2, then the kernel it clocked by 148.5 MHz, therefore LSPCLK is 37.125 MHz.
    I don't have fancy osciloscope, but I suppose it is able to measure difference between 9608 and 9705 Hz. Could you please give me piece of advice how to double check the baudrate on the SCI?
  • 0 in reply to Baranov Mihail
    TI__Genius 17315 points
    Baranov,

    Checking the baud rate could possibly be done by continuously transmitting AA or 55 (alternating 0 and 1) and measure with an oscilloscope. Also, you might want to check XCLKOUT, too.

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken
  • 0 in reply to Ken Schachter
    Intellectual 350 points

    I've just checked the baud-rate by transmitting 0x55 constantly. For better accuracy I changed acquire options in the osciloscope to averaging over 256 time-shots, it didn't help much, but the frequincy of this meandr is near 4808 Hz. Then I used FFT (it might helped better because it correlates sines/cosines over longer period of time), and that showed the same.

    Ken, I can't find in reference guides and datasheets what is the maximum possible  baudrate error in F28335 SCI? At what exact time SCI samples Framing-Error?

    Thank you

  • 0 in reply to Baranov Mihail
    TI__Genius 17315 points
    Baranov,

    Please see the "TMS320x2833x, 2823x Serial Communications Interface (SCI) Reference Guide" sprufz5:

    www.ti.com/lit/sprufz5

    On page 22, section 1.2.9 you will find table 1-5 which has percentage error for common SCI bit rates (based on 37.5 MHz LSPCLK clock frequency. This is the only reference that I can find for baud rate error.

    Though probably not related, I would to point out an SCI advisory in the Silicon Errata on page 9:

    www.ti.com/lit/sprz272

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken
  • 0 in reply to Ken Schachter
    Intellectual 350 points

    Thank you! It looks like I've got caught by the trap described in the errata.

    Don't know what to do now...