Part Number: TMS320F28335
Other Parts Discussed in Thread: TPS3306
Hello,
I (My customer) would have questions on the reset of the DSP TMS320F2833X.
From the datasheet the minimum operating voltage of these devices is 3,135V, as in the image below
The reset supervision circuit should theoretically release the reset signal when the supply voltage rises above this minimum voltage.
The SLVA296A document prescribes the use of a TPS3306-18 which is a double supervisor because it controls both the VDD (3.3V) and the VDD core (1.8V).
See below please:
The threshold voltage of this supervisor is 2.93V for the VDD, which is lower than the minimum working voltage of the DSP.
Theoretically it does not seem correct, am I mistaking something?
Could it be that if there is a typical 100ms delay before the reset is released, is it counted that in that period of time the voltage VDD has "reasonably" reached its stability?
This is a particular situation in customer application where the VDD (and also the VDD core) are given very slowly and I would therefore like to clarify the doubts on the above questions.
Many Thanks,
Antonio
