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TMS320F28377S: Issue CLA Writing to ePWM DBCTL Register

Jeramie Bianchi
Expert 3315 points

Part Number: TMS320F28377S

I believe that I have found a problem with configuring the ePWM DBCTL register from the CLA. I have not tested if the same problem shows up when writing the registers from the CPU.

 

It appears that if ePWM register DBCTL2 contains an 0x04 value and a CLA write of 0x00 is done to it the value of register DBCTL OUT_MODE field is set to 0x3.

 

Here is a CLA assembly example:

 

               ; --------------------

               ; This code sequence will produce bad value in DBCTL register

               ;

               MXOR32              MR0, MR0, MR0                              ; Zero

               MMOV16             @_EPwm1Regs.DBCTL, MR0        ; Zero

               MMOVXI              MR0, #4

               MMOV16             @_EPwm1Regs.DBCTL2, MR0     ; Set with SHDWDBCTLMODE enabled

               MXOR32              MR0, MR0, MR0                              ; Zero

               MMOV16             @_EPwm1Regs.DBCTL, MR0        ; Zero

               MMOV16             @_EPwm1Regs.DBCTL2, MR0     ; Set with SHDWDBCTLMODE enabled

 

               ; *** Error: At this point DBCTL is 0x03 when it should be 0x00. DBCTL2 is 0x00.

              

               ; --------------------

               ; The following code segments will all work

               ;

               MXOR32              MR0, MR0, MR0                              ; Zero

               MMOV16             @_EPwm1Regs.DBCTL, MR0        ; Zero

               MMOVXI              MR0, #0

               MMOV16             @_EPwm1Regs.DBCTL2, MR0     ; Set Zero

               MXOR32              MR0, MR0, MR0                              ; Zero

               MMOV16             @_EPwm1Regs.DBCTL, MR0        ; Zero

               MMOV16             @_EPwm1Regs.DBCTL2, MR0     ; Set with SHDWDBCTLMODE enabled

 

               ; Correct: At this point DBCTL is 0x00 and  DBCTL2 is 0x00.

 

               ; Just setting DBCTL2 to zero first before zeroing DBCTL works.

 

               MXOR32              MR0, MR0, MR0                              ; Zero

               MMOV16             @_EPwm1Regs.DBCTL2, MR0     ; Set Zero

               MMOV16             @_EPwm1Regs.DBCTL, MR0        ; Zero

 

               ; Correct: At this point DBCTL is 0x00 and  DBCTL2 is 0x00.

 

I would like to have this verified and an explanation for why writing to DBCTL2 register would change the value in DBCTL?

 

I would also like a list of other register write combinations that would show this same type of sequence initialization related issue?

 

Thanks

Jeramie

  • 0
    TI__Guru 52200 points

    Jeramie,

    I’ll take a look at this for you.

    Nima

  • 0 in reply to Nima Eskandari
    TI__Guru 52200 points
    you may know the answer to this off the top of your head.
  • 0 in reply to Nima Eskandari
    TI__Guru 52200 points
    Can you comment on this?
  • 0 in reply to Nima Eskandari
    TI__Guru 52200 points
    Still investigating this.
  • 0
    TI__Guru** 117001 points

    Hi,

    The scenario you are describing is somewhat confusing. In code below (where you see the problem) -

      ; --------------------

                   ; This code sequence will produce bad value in DBCTL register

                   ;

                   MXOR32              MR0, MR0, MR0                              ; Zero

                   MMOV16             @_EPwm1Regs.DBCTL, MR0        ; Zero

                   MMOVXI              MR0, #4

                   MMOV16             @_EPwm1Regs.DBCTL2, MR0     ; Set with SHDWDBCTLMODE enabled

                   MXOR32              MR0, MR0, MR0                              ; Zero

                   MMOV16             @_EPwm1Regs.DBCTL, MR0        ; Zero

                   MMOV16             @_EPwm1Regs.DBCTL2, MR0     ; Set with SHDWDBCTLMODE enabled

     

                   ; *** Error: At this point DBCTL is 0x03 when it should be 0x00. DBCTL2 is 0x00.

    You are writing 0x4 to DBCTL2 register which sets the SHDWDBCTLMODE bit to '1'. That means any further RD/WR access to DBCTL register will go to shadow register and not to actual DBCTL register. Later you write 0x0 to DBCTL register which will update the shadow register and not DBCTL register. Next you clear the DBCTL2 register to 0x0 means further RD/WR access will happen to DBCTL register and not shadow register. So after this you are actually reading DBCTL register where as 0x0 was written to shadow register. That's why you see different value. If you Ist clear the DBCTL2 register and then write 0x0 to DBCTL register then you don't see issue because in this case you are writing to same register which you are reading.

    Hope this clarifies the issue.

    Regards,

    Vivek Singh