CCS/TMS320F28035: Unwanted Loop back in SCI

Tool/software: Code Composer Studio

I am using TMS320F28035 SCI, in polling mode 115200 8 bit no parity mode without loopback. 

I am getting the same data which I am transmitting one by one byte on SciaRegs.SCIRXBUF register.

I checked TX and RX are not connected physically and it works correctly when the other processor when I am sending data back and forth on TX/RX using other processor. 

But when I removed the other processor free-ed up TX/RX lines. I am having this above issue.

Is the physical address of SCIRX and TX buffer the same ? How can I clear TX buffers after the data is transmitted ?

Thanks in advance.

signed int getchar(void)
{
	signed int	c = -1;
	
	// if there are any unread characters in the FIFO, get the first-in
	if (0 != SciaRegs.SCIFFRX.bit.RXFFST)
	{
		c = SciaRegs.SCIRXBUF.all;
	}
	else
	{
		c = -1;
		
		if (0 != SciaRegs.SCIRXST.bit.RXERROR)
		{
			SciaRegs.SCICTL1.bit.SWRESET = 0;
			SciaRegs.SCICTL1.all = 0x0023;
		}
	}
	
	return(c);
}


Sci_init()
{
        GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 0;            // function = GPIO
        GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 0;            // function = GPIO
        GpioCtrlRegs.GPAMUX1.bit.GPIO7  = 2;            // function = SCIRXDA
        GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2;            // function = SCITXDA

        SciaRegs.SCICTL1.bit.SWRESET = 0;               // Init SCI state machine

        // FIFO
        SciaRegs.SCIFFTX.all = 0xE040;                  // SCIRST | SCIFFENA | TXFIFOXRESET | TXFFINTCLR
        SciaRegs.SCIFFRX.all = 0x605f;//0x2044;         // RXFFIL = 15 | RXFFINTCLR | RXFIFORESET | RXFFOVRCLR
        SciaRegs.SCIFFCT.all = 0x0;                     // Auto Baud disabled
        SciaRegs.SCICCR.all  = 0x0007;                  // Character len = 8
        SciaRegs.SCICTL1.all = 0x0003;                  // TXENA | RXENA
        SciaRegs.SCIHBAUD    = 0;
        SciaRegs.SCILBAUD    = 15;                      // 48-38400 baud @LSPCLK = 15MHz

        SciaRegs.SCICTL1.all = 0x0023;                  // TXENA | RXENA | SW RESET

    EDIS;

    SciaRegs.SCIFFRX.bit.RXFIFORESET = 0;               // reset the FIFO pointer to zero
    SciaRegs.SCIFFRX.bit.RXFIFORESET = 1;               // re-enable receive FIFO operatio
}