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CCS/TMS320F28335: TMDSDOCK28335

SANDEEP KUMAR SAHOO
Prodigy 130 points

Part Number: TMS320F28335

Tool/software: Code Composer Studio

What is the meaning of " half " in

EPwm1Regs.TBPRD = 37500;

EPwm1Regs.CMPA.half.CMPA = EPwm1Regs.TBPRD / 2

EPwm1Regs.CMPB = EPwm1Regs.TBPRD / 4;

Why not with CMPB  ??

  • 0
    TI__Mastermind 42195 points

    Sandeep,

    "half" in the above referenced line of code is an mnemonic that allow you to access a struct.

    EPWM1Regs is a struct of type EPWM_REGS:

    EPWM_REGS is a Struct:

    One union in the EPWM_REGS struct is of type "CMPA_HRPWM_GROUP"(highlighted above). This union contains a struct of type"CMPA_HRPWM_REG" which is aliased to the mnemonic "half", which is what you are asking about above.

    You can see 'half' defined here: 

    The is simply a mnemonic and could be anything. The word 'half' was likely chosen because the two Uint16 variables within the "CMPA_HRPWM_REGS" struct are each  half of the entire register.

    CMPB does not have the same union, it is simply a Uint16... CMPA.half has "CMPA" and "CMPAHR".


    Regards,
    Cody 

  • 0 in reply to Cody Watkins
    Prodigy 130 points

    Please ellaborate it clearly. Unable to get you. Why half is not written in "// EPWM Module 1 config " with CMPA but written in  "// EPWM Module 2 config "??

    // EPWM Module 1 config
    EPwm1Regs.TBPRD = 1200; // Period = 1201 TBCLK counts
    EPwm1Regs.CMPA = 600; // Set 50% fixed duty for EPWM1A
    EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Asymmetrical mode
    EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Master module
    EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module
    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
    EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // set actions for EPWM1A
    EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
    EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
    EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
    EPwm1Regs.DBFED = 50; // FED = 50 TBCLKs initially
    EPwm1Regs.DBRED = 70; // RED = 70 TBCLKs initially

    // EPWM Module 2 config
    EPwm2Regs.TBPRD = 1200; // Period = 1201 TBCLK counts
    EPwm2Regs.CMPA.half.CMPA = 600; // Set 50% fixed duty EPWM2A
    EPwm2Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero initially
    EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Asymmetrical mode
    EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
    EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
    EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
    EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
    EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
    EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET; // set actions for EPWM2A
    EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;
    EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
    EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
    EPwm2Regs.DBFED = 30; // FED = 30 TBCLKs initially
    EPwm2Regs.DBRED = 40; // RED = 40 TBCLKs initially

  • 0 in reply to SANDEEP KUMAR SAHOO
    TI__Mastermind 42195 points
    Sandeep,
    the bit fields were done this way because the 'CMPA' also has some bits that only pertain to the HR portion of the module. The word "half" was chosen because the bit fields were exactly half of the total register size.

    These names are just mnemonics defined in the header files. If you go modify the structs you could modify "half" to be any string you wish, or even remove it all together.

    Regards,
    Cody