We are trying to assess the ability to detect bit state changes due to soft errors using the ECC and parity protection mechanisms built into the microcontroller. In this case, the kind of soft errors I'm referring to are described in section 3.4.1 of SPRACC0.
The combination of sections 2 and 3.4.1 of SPRACC0 describe the physical layout of the SRAM and how close any two bits in a word may be near each other. In order to assess the susceptibility of a single charged particle affecting multiple nearby bits, what are the number of rows in the SRAM array and the process node used in this memory? I have not been able to find this information in any literature and it would be very helpful to understand what additional software protections are needed to detect changes.
