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LAUNCHXL-F28379D: ePWM 3-phase: TBPHS register not shifting as expected.

Ben McCornack
Prodigy 10 points
Part Number: LAUNCHXL-F28379D

Hello,

I am trying to create a synchronized 3 phase output which will be fed to an inverter. 

Right now my code runs and produces 3 phases of output and I can shift phases 2 and 3 just fine. However, I have to shift it twice as many clock cycles as I would expect to create 120 degree phase shift.

For each phase TBPRD = 600. So, I'm pretty sure I should have set TBPHS = 200 for the second phase and TBPHS = 400 for the third phase...

However, when I do this I only get a phase shift of 60 degrees for each phase. When I double TBPHS for phase 2 and phase 3; they get shifted correctly. However, now phase 3 which has been shifted 800 clocks (even though the period is only 600) the output cuts to 0V for the last 1/3 of the period. 

I believe the problem is that TBPHS > TBPRD for the third phase. However, it is the only way that I have found to shift the output of each phase 120 degrees apart from one another.

Here is my code to set up the control registers for each ePWM:

EPwm1Regs.TBCTL.bit.FREE_SOFT = 0x11; 
EPwm1Regs.TBCTL.bit.PHSDIR = 0x0;
EPwm1Regs.TBCTL.bit.CLKDIV = 0x000;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0x000;
EPwm1Regs.TBCTL.bit.SWFSYNC = 0x0;
EPwm1Regs.TBCTL.bit.SYNCOSEL = 0x01;
EPwm1Regs.TBCTL.bit.PRDLD = 0x0;
EPwm1Regs.TBCTL.bit.PHSEN = 0x0;
EPwm1Regs.TBCTL.bit.CTRMODE = 0x10;  //UP-DOWN

EPwm1Regs.TBCTR = 0x0000; // Clear timer counter
EPwm1Regs.TBPRD = PRDa;  //PRDa = 600
EPwm1Regs.TBPHS.bit.TBPHS = 0x0000;

EPwm2Regs.TBCTL.bit.FREE_SOFT = 0x11;
EPwm2Regs.TBCTL.bit.PHSDIR = 0x0;
EPwm2Regs.TBCTL.bit.CLKDIV = 0x000;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0x000;
EPwm2Regs.TBCTL.bit.SWFSYNC = 0x0;
EPwm2Regs.TBCTL.bit.SYNCOSEL = 0x00;
EPwm2Regs.TBCTL.bit.PRDLD = 0x1;
EPwm2Regs.TBCTL.bit.PHSEN = 0x1;
EPwm2Regs.TBCTL.bit.CTRMODE = 0x11;  //UP-DOWN

EPwm2Regs.TBCTR = 0x0000;
EPwm2Regs.TBPRD = PRDa;     //PRDa = 600
EPwm2Regs.TBPHS.bit.TBPHS = PhaseB; //should be 200?

EPwm3Regs.TBCTL.bit.FREE_SOFT = 0x11;
EPwm3Regs.TBCTL.bit.PHSDIR = 0x0;
EPwm3Regs.TBCTL.bit.CLKDIV = 0x000; //possible location of error
EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0x000;
EPwm3Regs.TBCTL.bit.SWFSYNC = 0x0;
EPwm3Regs.TBCTL.bit.SYNCOSEL = 0x00;
EPwm3Regs.TBCTL.bit.PRDLD = 0x1;
EPwm3Regs.TBCTL.bit.PHSEN = 0x1;
EPwm3Regs.TBCTL.bit.CTRMODE = 0x11;  //UP-DOWN


EPwm3Regs.TBCTR = 0x0000;
EPwm3Regs.TBPRD = PRDa; //PRDa = 600
EPwm3Regs.TBPHS.bit.TBPHS = PhaseC; //Should be 400??

  • 0
    TI__Guru 57255 points

    Hi Ben,

    A few comments:

    1) For this device, the maximum speed at which the ePWM peripheral can be clocked is 100MHz.  You can see this constraint in the device datasheet labelled as f(EPWM).  You can have TBCTL[CLKDIV] and TBCTL[HSPCLKDIV] as 0.  However, you will have to have ClkCfgRegs.PERCLKDIVSEL[EPWMCLKDIV] as 1 (which is its default).  This all directly means that TBCLK, etc will increment in 1/100MHz steps - and you'll need to think about TBPRD in this way, too.

    2) I see that you've configured your ePWM in up-down count mode.  This means that along with setting TBPHS, you should also be thinking about how you'll want TBCTL[PHSDIR] configured.  With this hint, I believe you'll be able to figure out how to resolve your current issue.
         - Note that in general usage, you'd not want to set TBPHS greater than TBPRD.


    Hopefully this helps!


    Thank you,
    Brett