Tool/software: Code Composer Studio
Hi;
We are using the ECAP module of 280049,We creat a demo to test .Some problems we don't understand.
the code as follows,the ECAP4 can't capture value use this code,the ECAP1-3 did .if change InputXbarRegs:ECAP1 use INPUT6,EAP2-4 use INPUT3-5,then ECAP1 can't capture value,EAP2-4 did.
what's wrong with it ?
EALLOW;
InputXbarRegs.INPUT3SELECT = 13 ;
GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pullup on GPIO13
GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 0; // Synch to SYSCLKOUT
ECap1Regs.ECCTL0.bit.INPUTSEL = 3; // Select eCAP1 TO INPU13
InputXbarRegs.INPUT4SELECT = 12 ;
GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pullup on GPIO12
GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 0; // Synch to SYSCLKOUT
ECap2Regs.ECCTL0.bit.INPUTSEL = 4; // Select eCAP2 TO INPU12
InputXbarRegs.INPUT5SELECT = 13 ;
GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pullup on GPIO13
GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 0; // Synch to SYSCLKOUT
ECap3Regs.ECCTL0.bit.INPUTSEL = 5; // Select eCAP3 TO INPU16
InputXbarRegs.INPUT6SELECT = 12 ;
GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pullup on GPIO12
GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 0; // Synch to SYSCLKOUT
ECap4Regs.ECCTL0.bit.INPUTSEL = 6; // Select eCAP4 TO INPU12
//2.Init Regs .Ecap1-4
ECap1Regs.ECEINT.all = 0x0000; // Disable all capture interrupts
ECap1Regs.ECCLR.all = 0xFFFF; // Clear all CAP interrupt flags
ECap1Regs.ECCTL1.bit.CAP1POL = 0;
ECap1Regs.ECCTL1.bit.CAP2POL = 1;
ECap1Regs.ECCTL1.bit.CAP3POL = 0;
ECap1Regs.ECCTL1.bit.CAP4POL = 1;
ECap1Regs.ECCTL1.bit.CTRRST1 = 1;
ECap1Regs.ECCTL1.bit.CTRRST2 = 1; // Difference operation
ECap1Regs.ECCTL1.bit.CTRRST3 = 1; // Difference operation
ECap1Regs.ECCTL1.bit.CTRRST4 = 1; // Difference operation
ECap1Regs.ECCTL1.bit.CAPLDEN = 1; // Enable capture units
ECap1Regs.ECCTL1.bit.FREE_SOFT = 3;
ECap1Regs.ECCTL2.bit.CAP_APWM = 0; //ECAP;
ECap1Regs.ECCTL2.bit.SYNCI_EN = 0; // Enable sync in
ECap1Regs.ECCTL2.bit.SYNCO_SEL = 2; // Pass through
ECap1Regs.ECCTL2.bit.TSCTRSTOP = 1; // Start Counter
ECap1Regs.ECCTL2.bit.REARM = 1; // arm one-shot
ECap1Regs.ECEINT.bit.CEVT4 = 0; // 4 events = interrupt
ECap1Regs.ECCTL2.bit.STOP_WRAP = 3;
ECap2Regs.ECEINT.all = 0x0000; // Disable all capture interrupts
ECap2Regs.ECCLR.all = 0xFFFF; // Clear all CAP interrupt flags
ECap2Regs.ECCTL1.bit.CAP1POL = 0;
ECap2Regs.ECCTL1.bit.CAP2POL = 1;
ECap2Regs.ECCTL1.bit.CAP3POL = 0;
ECap2Regs.ECCTL1.bit.CAP4POL = 1;
ECap2Regs.ECCTL1.bit.CTRRST1 = 1;
ECap2Regs.ECCTL1.bit.CTRRST2 = 1; // Difference operation
ECap2Regs.ECCTL1.bit.CTRRST3 = 1; // Difference operation
ECap2Regs.ECCTL1.bit.CTRRST4 = 1; // Difference operation
ECap2Regs.ECCTL1.bit.CAPLDEN = 1; // Enable capture units
ECap2Regs.ECCTL1.bit.FREE_SOFT = 3;
ECap2Regs.ECCTL2.bit.CAP_APWM = 0; //ECAP;
ECap2Regs.ECCTL2.bit.SYNCI_EN = 0; // Enable sync in
ECap2Regs.ECCTL2.bit.SYNCO_SEL = 2; // Pass through
ECap2Regs.ECCTL2.bit.TSCTRSTOP = 1; // Start Counter
ECap2Regs.ECCTL2.bit.REARM = 1; // arm one-shot
ECap2Regs.ECEINT.bit.CEVT4 = 1; // 4 events = interrupt
ECap2Regs.ECCTL2.bit.STOP_WRAP = 3;
ECap3Regs.ECEINT.all = 0x0000; // Disable all capture interrupts
ECap3Regs.ECCLR.all = 0xFFFF; // Clear all CAP interrupt flags
ECap3Regs.ECCTL1.bit.CAP1POL = 0;
ECap3Regs.ECCTL1.bit.CAP2POL = 1;
ECap3Regs.ECCTL1.bit.CAP3POL = 0;
ECap3Regs.ECCTL1.bit.CAP4POL = 1;
ECap3Regs.ECCTL1.bit.CTRRST1 = 1;
ECap3Regs.ECCTL1.bit.CTRRST2 = 1; // Difference operation
ECap3Regs.ECCTL1.bit.CTRRST3 = 1; // Difference operation
ECap3Regs.ECCTL1.bit.CTRRST4 = 1; // Difference operation
ECap3Regs.ECCTL1.bit.CAPLDEN = 1; // Enable capture units
ECap3Regs.ECCTL1.bit.FREE_SOFT = 3;
ECap3Regs.ECCTL2.bit.CAP_APWM = 0; //ECAP;
ECap3Regs.ECCTL2.bit.SYNCI_EN = 0; // Enable sync in
ECap3Regs.ECCTL2.bit.SYNCO_SEL = 2; // Pass through
ECap3Regs.ECCTL2.bit.TSCTRSTOP = 1; // Start Counter
ECap3Regs.ECCTL2.bit.REARM = 1; // arm one-shot
ECap3Regs.ECEINT.bit.CEVT4 = 1; // 4 events = interrupt
ECap3Regs.ECCTL2.bit.STOP_WRAP = 3;
ECap4Regs.ECEINT.all = 0x0000; // Disable all capture interrupts
ECap4Regs.ECCLR.all = 0xFFFF; // Clear all CAP interrupt flags
ECap4Regs.ECCTL1.bit.CAP1POL = 0;
ECap4Regs.ECCTL1.bit.CAP2POL = 1;
ECap4Regs.ECCTL1.bit.CAP3POL = 0;
ECap4Regs.ECCTL1.bit.CAP4POL = 1;
ECap4Regs.ECCTL1.bit.CTRRST1 = 1;
ECap4Regs.ECCTL1.bit.CTRRST2 = 1; // Difference operation
ECap4Regs.ECCTL1.bit.CTRRST3 = 1; // Difference operation
ECap4Regs.ECCTL1.bit.CTRRST4 = 1; // Difference operation
ECap4Regs.ECCTL1.bit.CAPLDEN = 1; // Enable capture units
ECap4Regs.ECCTL1.bit.FREE_SOFT = 3;
ECap4Regs.ECCTL2.bit.CAP_APWM = 0; //ECAP;
ECap4Regs.ECCTL2.bit.SYNCI_EN = 0; // Enable sync in
ECap4Regs.ECCTL2.bit.SYNCO_SEL = 2; // Passx through
ECap4Regs.ECCTL2.bit.TSCTRSTOP = 1; // Start Counter
ECap4Regs.ECCTL2.bit.REARM = 1; // arm one-shot
ECap4Regs.ECEINT.bit.CEVT4 = 1; // 4 events = interrupt
ECap4Regs.ECCTL2.bit.STOP_WRAP = 3;
EDIS;
thanks !
