Other Parts Discussed in Thread: TMS320F28044
I am doing an ultrasound design using a TMS320F28044. My need is to generate a chirp waveform, and then after a suitable delay start sampling the received waveform using the ADC.
In connection with this, I need to have a repeatable phase difference between the rising edge of the ADC clock relative to a start signal from one measurement cycle to another.
From what I read, the ADC clock is the result of dividing the sysclk. It appears as if this divider/counter is free-running. The question, therefore, is whether I can place the divider/counter in a known state, and then selectively assert ADCCLKEN so as to control the phase of the rising edge of the ADC clock for any measurement cycle.
Thanks,
Art