Part Number: TMS320F28379S
Tool/software: Code Composer Studio
A problem occur, when i use Ramp Generator in CMPSS Subsystem to generate a slope voltage. I set "Cmpss1Regs.COMPDACCTL.bit.RAMPSOURCE = 6" and i need a interrupt on TBCTR=CMPA in ePWM7. But when i ENABLE the ePWM7's interrupt, the Cmpss1Regs.RAMPSTS is unchanged；when i DISABLE the ePWM7's interrupt, the Cmpss1Regs.RAMPSTS decreased；
I want to know the reason for this phenomenon. Is there any problem with my code?
my code is fallowed.
void ePwmConfigForCOT( void ) {
InitEPwm7Gpio();
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
EALLOW;
// This is needed to write to EALLOW protected registers
PieVectTable.EPWM7_INT = &epwm7_isr;
EDIS;
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
// //Configure EPWM to run at SYSCLK
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 0;
EPwm7Regs.TBCTL.bit.CLKDIV = 0;
EPwm7Regs.TBCTL.bit.HSPCLKDIV = 0;
EPwm7Regs.TBPRD = 5000; // Set timer period
EPwm7Regs.TBPHS.all = 0; // Phase is 0
EPwm7Regs.TBCTR = 0;
// Setup TBCLK
EPwm7Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm7Regs.TBCTL.bit.PHSEN = TB_ENABLE; // when sync comes, TBCTR=TBPHS
//EPwm1Regs.TBCTL.bit.SYNCOSEL = 1; // These bits select the source of the EPWMxSYNCO signal. 0 means EPWMxSYNC
// EPwm7Regs.HRPCTL.bit.PWMSYNCSEL = 1; // 0 PWMSYNC = PRD_eq signal pulse 1 PWMSYNC = CNT_zero signal pulse
//EPwm1Regs.TBCTL.bit.FREE_SOFT=0x0;
// SyncSocRegs.SYNCSELECT.bit.EPWM7SYNCIN = 6; // 0：EPWM7SYNCOUT
EPwm7Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // These bits select the source of the EPWMxSYNCO signal. 0 means EPWMxSYNC TB_SYNC_IN
// TB_SYNC_IN=0 TB_CTR_ZERO
EPwm7Regs.TBCTL.bit.HSPCLKDIV = 0 ; // Clock ratio to SYSCLKOUT
EPwm7Regs.TBCTL.bit.CLKDIV = 0;
// TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV)
EPwm7Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
// EPwm7Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm7Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
// EPwm7Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare
EPwm7Regs.CMPA.bit.CMPA = 55; // 40/8*(10^7) = 500ns
EPwm7Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM1A on CAU 当CTR=0时，强制EPWM1A输出高电平
EPwm7Regs.AQCTLA.bit.CAU = AQ_CLEAR; // 当CTR=CMPA且计数器CTR增计数时，强制EPWM1A输出低电平
// EPwm7Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // Set PWM1A on CAU 当CTR=0时，强制EPWM1A输出高电平
// EPwm7Regs.AQCTLB.bit.CAU = AQ_SET; // 当CTR=CMPA且计数器CTR增计数时，强制EPWM1A输出低电平
// Active Low PWMs - Setup Deadband
EPwm7Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm7Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm7Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm7Regs.DBRED.bit.DBRED = 5;
EPwm7Regs.DBFED.bit.DBFED = 10;
EDIS;
EALLOW;
// EPwmXbarRegs
EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX0 = 0; // CMPSS1.CTRIPH -> MUX0 output -> TRIP4MUXENABLE switch
EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX0 = 1; // TRIP4MUXENABLE enables MUX0
EPwmXbarRegs.TRIPOUTINV.bit.TRIP4 = 0; // Active high
EPwm7Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_TRIPIN4; // DCAH = Comparator 1 output DCAH的电平高低由比较器1的输出决定
// EPwm7Regs.DCTRIPSEL.bit.DCALCOMPSEL = DC_TZ2; // DCAL = TZ2 DCAL的电平高低由TZ2决定
EPwm7Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCAH_HI; // DCAEVT1 = DCAH High(will become active as Comparator output goes high)
// // DCAH高电平时产生DCAEVT1事件
//
// EPwm7Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT_FLT;
EPwm7Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT1; //
EPwm7Regs.DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC; // Take async path
EPwm7Regs.DCACTL.bit.EVT1SYNCE = 1; // // Sync enabled:
// // With DCAEVT1 sync: 166 ns delay. With trip: 31 ns
EPwm7Regs.TZCTL.bit.DCAEVT1 = TZ_NO_CHANGE;
//===========================================================================
// Event Filtering Configuration for DCAEVT1 (disabled for now)
EPwm7Regs.DCFCTL.bit.SRCSEL = DC_SRC_DCAEVT1;
EPwm7Regs.DCFCTL.bit.BLANKE = DC_BLANK_DISABLE;
EPwm7Regs.DCFCTL.bit.PULSESEL = DC_PULSESEL_ZERO; //Pulse Select For Blanking & Capture Alignment
EPwm7Regs.DCFCTL.bit.BLANKINV = 0;
EPwm7Regs.DCFOFFSET = 0; // Blanking Window Offset = CMPA(n+1)
EPwm7Regs.DCFWINDOW = 100; // Blanking window length - initial value
//===========================================================================
//EPwm7Regs.TZFLG.bit.DCAEVT1
//EPwm7Regs.TZCLR.bit.DCAEVT1
EDIS;
// Interrupt where we will change the Compare Values
EPwm7Regs.ETSEL.bit.INTSEL = ET_CTRU_CMPA; // Select INT on Zero event
// EPwm7Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm7Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1th event
EPwm7Regs.ETSEL.bit.INTEN = 1; // Enable INT
// Step 5. User specific code, enable interrupts:
// Enable CPU INT3 which is connected to EPWM1-12 INT:
//IER |= M_INT3;
// Enable EPWM INTn in the PIE: Group 3 interrupt 1-12
//PieCtrlRegs.PIEIER3.bit.INTx7 = 1;
EALLOW;
GpioCtrlRegs.GPBGMUX2.bit.GPIO52 = 01; //
GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 01; //gpio60 -> OUTPUTXBAR3 (O)
//
// Configure CTRIPOUTH output pin
// Configure OUTPUTXBAR3 to be CTRIPOUT1H
//
SyncSocRegs.SYNCSELECT.bit.SYNCOUT = 2; // 0：EPWM7SYNCOUT
OutputXbarRegs.OUTPUT1MUX0TO15CFG.bit.MUX14 = 3;
//
//Enable OUTPUTXBAR3 Mux for Output
//
OutputXbarRegs.OUTPUT1MUXENABLE.bit.MUX0 = 1;
EDIS;
}
void CmpssConfigForCOT( void ) {
// GPIO_SetupPinMux(GPIO_CTRIP_PIN_NUM, GPIO_MUX_CPU1, GPIO_CTRIP_PER_NUM);
// GPIO_SetupPinMux(GPIO_CTRIPOUT_PIN_NUM, GPIO_MUX_CPU1,
// GPIO_CTRIPOUT_PER_NUM);
EALLOW;
GpioCtrlRegs.GPBGMUX2.bit.GPIO60 = 01; //
GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 01; //gpio60 -> OUTPUTXBAR3 (O)
// GpioCtrlRegs.GPBDIR.bit.GPIO60 =
EDIS;
EALLOW;
// CpuSysRegs.PCLKCR0.bit.ADCENCLK = 1;
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
// AdcRegs.ADCCTL1.bit.ADCBGPWD = 1;
DELAY_US(1000);
//
//Enable CMPSS
//
Cmpss1Regs.COMPCTL.bit.COMPDACE = 1;
//
//NEG signal comes from DAC
//
Cmpss1Regs.COMPCTL.bit.COMPHSOURCE = NEGIN_DAC;
//
//Use VDDA as the reference for DAC
//
Cmpss1Regs.COMPDACCTL.bit.SELREF = REFERENCE_VDDA;
Cmpss1Regs.COMPDACCTL.bit.DACSOURCE = 1; // DACHVALA is updated from the ramp generator
Cmpss1Regs.COMPDACCTL.bit.RAMPSOURCE = 6; // n-1 ----> PWMSYNCn
// Cmpss1Regs.COMPDACCTL.bit.RAMPLOADSEL = 1;
// Cmpss1Regs.COMPDACCTL.bit.SWLOADSEL = 1;
//
//Set DAC to midpoint for arbitrary reference
//
//Cmpss1Regs.DACHVALS.bit.DACVAL = 2048;
Cmpss1Regs.RAMPMAXREFS = (Uint16)( 2048 << 4 );
Cmpss1Regs.RAMPDECVALS = 2;
Cmpss1Regs.RAMPDLYS.bit.DELAY = 30;
Cmpss1Regs.COMPHYSCTL.bit.COMPHYS = 4; // 2 Set to 2x of typical hysteresis
//
// Configure CTRIPOUT path
// Asynch output feeds CTRIPH and CTRIPOUTH
//
Cmpss1Regs.COMPCTL.bit.CTRIPHSEL = CTRIP_ASYNCH;
Cmpss1Regs.COMPCTL.bit.CTRIPOUTHSEL = CTRIP_ASYNCH;
//
// Configure CTRIPOUTH output pin
// Configure OUTPUTXBAR3 to be CTRIPOUT1H
//
OutputXbarRegs.OUTPUT3MUX0TO15CFG.bit.MUX0 = 0;
//
//Enable OUTPUTXBAR3 Mux for Output
//
OutputXbarRegs.OUTPUT3MUXENABLE.bit.MUX0 = 1;
// Cmpss1Regs.COMPCTL.bit.COMPDACE = 1;
EDIS;
}
__interrupt void epwm7_isr( void ) {
// Clear INT flag for this timer
EPwm7Regs.ETCLR.bit.INT = 1;
if( Cmpss1Regs.COMPSTS.bit.COMPHSTS == 1 ) {
// EPwm1Regs.TZFRC.bit.DCAEVT1 = 1;
EPwm7Regs.TBCTL.bit.SWFSYNC = 1;
}
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
