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TMS320F28235: PWM interrupt trigger problem of TI28235

Annie Liu
Genius 10295 points
Part Number: TMS320F28235

Hi 

Problem background: It was found that PWM interrupt could not be entered without and power-down again, after an online upgrade of TI28235 program using CAN BOOTLOADER. By analyzing the cause, it was found that the ETFLG flag corresponding to the PWM interrupt was not cleared inside the PWM initialization.

Question (1): Since the ETFLG logo is always there, why is it impossible to get into the PWM interrupt program?

Question (2): Is it because PWM's interrupt request to the CPU is a pulse signal? It is described in the TI technical documentation as:

If interrupts are enabled ,ETSEL[INTEN]=1 and the interrupt flag is clear,ETFLG[INT]=0, then an interrupt pulse is generated and the interrupt flag is set, ETFLG[INT]=1.    

So how long does this pulse signal last?

Thanks.

  • 0
    TI__Guru 60865 points

    Hi Annie,

    You do indeed need to clear ETFLG.INT before additional ISRs can be generated.  The documentation also says that an additional ISR can be pending and will go through as soon as the INT flag is cleared.

  • 0 in reply to Devin Cottier
    TI__Genius 10295 points

    Hi Devin,

    Thanks for your answer. And the customer also have the problem for PWM interrupt. I would appreciate it if you could help to answer it.

    First, there is an operation to clear ETFLG.INT in his ISR interrupt program. Under normal circumstances, the ISR interrupt program can run according to the PWM interrupt cycle.
    Second, his PWM initialization program does not clear ETFLG.INT. In this case, after the CAN BOOTLOADER is upgraded, the interrupt program cannot be entered.
    What is the reason for this phenomenon. Since ETFLG.INT is always 1, why not enter the ISR interrupt, then ETFLG.INT can be cleared in the ISR interrupt.

    Thanks.

  • 0 in reply to Annie Liu
    TI__Guru 60865 points
    Hi Annie,

    Based on the bit description above, the ISR will not be generated just because the bit is '1'. The ISR is only generated (1) when the bit is '0' and a new ISR trigger occurs or (2) The bit was already set --> a new ISR trigger occurs --> the new ISR is set to pending --> the bit is cleared --> The pending ISR is now allowed to propagate

    In either case, something always needs to clear the flag before additional ISRs can occur. The customer will either need to ensure that the ePWM is shut-down and all pending ISRs are cleared before branching to updated firmware and/or they should make sure any pending INT flags are cleared during ePWM re-initialization.