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TMS320F280041: TMS320F280041 - /CS timing in SPI mode 1 with ADS114S08B

mirkoc
Prodigy 60 points
Part Number: TMS320F280041
Other Parts Discussed in Thread: ADS114S08B,

Hi,

we have implemented an input acquisition system based on the ADC ADS114S08B, connected to the TMS320F280041 DSP by SPI.


We are trying to use the 4-wire SPI configuration (/CS SCLK MISO MOSI) in the SPI mode 1 (CPOL = 0, CPHA = 1) as suggesten in the ADC datasheet. In this condition the /CS is tied to Hi-Level until the last SCLK rising edge and it is released after a not predicible delay time from this edge. In the ADS114S08B is required that this delay time of CS rising edge must excede the finel SCLK falling edge of at least 20ns. How it possible to ensure this condition in the TMS320F280041? Using the required SPI mode 1, the /CS goes low befor the last SCLK falling edge.

We know that we could drive the /CS as GPIO or tied it always to GND, but we think these could be workarounds, not the right solution.

Thanks!

  • 0
    TI__Guru 55700 points
    Mirkoc,

    I'm currently held up with some urgent commitment. I shall get back with you in next couple of business days.

    Regards,
    Manoj
  • 0 in reply to Manoj Santha Mohan
    TI__Guru 55700 points
    Mirkoc,

    F280041 SPI does indeed support SPI mode 1 (CPOL = 0, CPHA = 1). I believe you are planning to configure F280041 SPI is master mode.
    If so, please check SPI Master Mode Switching Characteristics (Clock Phase 1) and SPI Master Mode Timing Requirements in F280041 DS.

    Please check parameter 23 of SPI Master Mode Switching Characteristics (Clock Phase 1). Based on what I see meeting 20ns requirement shouldn't be a problem.

    Regards,
    Manoj
  • 0 in reply to Manoj Santha Mohan
    Prodigy 60 points
    Hi Manoj,

    I think that the problem was a different interpretation of the "SPI mode 1" mode of the DSP compared to the ADC. Specifically, taking a look at the timing graphs the clock phase = 1 reported in ADC is optained by setting Clock Phase = 0 in the DSP.

    I have tried to set both clock polarity and clock phase = 0 and it seems work fine.

    Regards.