Tool/software: Code Composer Studio
Hi ,
I am trying to demonstrate the ePWM operation using base address and offset . I have done all configuration carefully.
But i have some issue. I can set all specific register regarding ePWM configration but i am not able to set CMPA register.
Also there is issue is that TBCTR reg. TBCTR is not starting the counting.
Can you suggest what may wrong ?
void ePWM_Init(void)
{
//------------------------------------------------------------------------------
EALLOW;
/*Provide the clock for 12 epwm's pins in CPUSYS_CFG*/
HWREGH(CPUSYS_BASE + PCLKCR2) = 0x00000FFF;
EDIS;
ePWM1_Gpio();
/*Load user ISR function to vct table to get called at proper events*/
Interrupt_register(INT_EPWM1 , &epwm1_isr );
/*Enable the Module group interrupt */
Interrupt_enable(INT_EPWM1);
/* ePWM_1 is initialize with ePWM interrupt */
EALLOW;
// Configure the prescaler to the ePWM modules.
HWREGH(CLKCFG_BASE + PERCLKDIVSEL) |= ( PLLSYSCLK_1 << 0) ; // PLLSYSCLK_0 = /1 of PLLSYSCLK
// PLLSYSCLK_1 = /2 of PLLSYSLCK (default on reset)
EDIS;
/* clear timer counter */
HWREGH( EPWM1_BASE + TBCTR) = 0x0000;
/* Set timer period */
HWREGH( EPWM1_BASE + TBPRD) = Timer_Period ;
/* Set timer phase */
HWREGH( EPWM1_BASE + TBPHS) = 0U; // Disable phase
/*clear before settings done*/
HWREGH( EPWM1_BASE + TBCTL) = 0U;
/* Configure timer control register */
HWREGH( EPWM1_BASE + TBCTL) |= ((TB_COUNT_UP << 0) | (CLKDIV << 10) | (HSPCLKDIV << 7) | (0U << 2));
//HWREGH( EPWM1_BASE + CMPCTL ) = 0U;
/* Setup shadow register load on ZERO */
HWREGH( EPWM1_BASE + CMPCTL ) |= ( (CC_CTR_ZERO_PRD << 0) | ( CC_CTR_ZERO << 2) | ( CC_IMMEDIATE << 4) | ( CC_IMMEDIATE << 6)) ;
/* Set Compare values */
HWREGH( EPWM1_BASE + CMPA ) = (uint16_t)(0x01f40000);
/* Action Qualifier Control - A */
HWREGH( EPWM1_BASE + AQCTLA) |= ( ( AQ_SET << 4) | ( AQ_CLEAR << 6) ); // ePWM1_A CAU = Set and CAD = Clear
/* Action Qualifier Control - B */
HWREGH( EPWM1_BASE + AQCTLB) |= ( ( AQ_SET << 8) | ( AQ_CLEAR << 10) ); // ePWM1_B
// Interrupt
/* Generate INT on 3rd event*/
/* Select INT on Zero event */
// 001: Enable event time-base counter equal to zero
HWREGH( EPWM1_BASE + ETSEL) |= ( (ET_CTR_PRD << 0) | ( 1U << 3) ) ;
HWREGH( EPWM1_BASE + ETPS) |= ( ET_3RD << 0) ;
/*-------------------------------------------------------------------------------------------------*/
}
interrupt void epwm1_isr(void)
{
EALLOW;
/* Interrupt Clear */
HWREGH( EPWM1_BASE + ETCLR ) |= ( 1U << 0);
/* Acknowledge this interrupt to receive more interrupts from group 3 */
//HWREGH( PIECTRL_BASE + PIEACK ) |= (1U << 2);
Interrupt_Clear_PIEACK();
EDIS;
}
void ePWM1_Gpio(void)
{
EALLOW;
HWREGH( GPIOCTRL_BASE + GPAGMUX1 ) |= (( 0 << 0) | ( 0 << 2));
HWREGH( GPIOCTRL_BASE + GPAMUX1 ) |= (( 1 << 0) | ( 1 << 2));
HWREGH( GPIOCTRL_BASE + GPAPUD ) |= (( 1U << 0 ) | ( 1U << 1));
EDIS;
}
