Other Parts Discussed in Thread: C2000WARE
Tool/software: Code Composer Studio
Hi all,
I have problems configuring the watchdog module in this specific device: here are my definitions:
/* PLL Status Register */
struct PLLSTS_BITS { /* bits description */
uint16_t PLLLOCKS:1; /* 0 PLL lock status */
uint16_t rsvd1:1; /* 1 reserved */
uint16_t PLLOFF:1; /* 2 PLL off bit */
uint16_t MCLKSTS:1; /* 3 Missing clock status bit */
uint16_t MCLKCLR:1; /* 4 Missing clock clear bit */
uint16_t OSCOFF:1; /* 5 Oscillator clock off */
uint16_t MCLKOFF:1; /* 6 Missing clock detect */
uint16_t DIVSEL:2; /* 7 Divide Select */
uint16_t rsvd2:7; /* 15:7 reserved */
};
union PLLSTS_REG {
uint16_t all;
struct PLLSTS_BITS bit;
};
/* High speed peripheral clock register bit definitions: */
struct HISPCP_BITS { /* bits description */
uint16_t HSPCLK:3; /* 2:0 Rate relative to SYSCLKOUT */
uint16_t rsvd1:13; /* 15:3 reserved */
};
union HISPCP_REG {
uint16_t all;
struct HISPCP_BITS bit;
};
/* Low speed peripheral clock register bit definitions: */
struct LOSPCP_BITS { /* bits description */
uint16_t LSPCLK:3; /* 2:0 Rate relative to SYSCLKOUT */
uint16_t rsvd1:13; /* 15:3 reserved */
};
union LOSPCP_REG {
uint16_t all;
struct LOSPCP_BITS bit;
};
/* Peripheral clock control register 0 bit definitions: */
struct PCLKCR0_BITS { /* bits description */
uint16_t rsvd1:2; /* 1:0 reserved */
uint16_t TBCLKSYNC:1; /* 2 EWPM Module TBCLK enable/sync */
uint16_t ADCENCLK:1; /* 3 Enable high speed clk to ADC */
uint16_t I2CAENCLK:1; /* 4 Enable SYSCLKOUT to I2C-A */
uint16_t SCICENCLK:1; /* 5 Enalbe low speed clk to SCI-C */
uint16_t rsvd2:2; /* 7:6 reserved */
uint16_t SPIAENCLK:1; /* 8 Enable low speed clk to SPI-A */
uint16_t rsvd3:1; /* 9 reserved */
uint16_t SCIAENCLK:1; /* 10 Enable low speed clk to SCI-A */
uint16_t SCIBENCLK:1; /* 11 Enable low speed clk to SCI-B */
uint16_t MCBSPAENCLK:1; /* 12 Enable low speed clk to McBSP-A */
uint16_t MCBSPBENCLK:1; /* 13 Enable low speed clk to McBSP-B */
uint16_t ECANAENCLK:1; /* 14 Enable system clk to eCAN-A */
uint16_t ECANBENCLK:1; /* 15 Enable system clk to eCAN-B */
};
union PCLKCR0_REG {
uint16_t all;
struct PCLKCR0_BITS bit;
};
/* Peripheral clock control register 1 bit definitions: */
struct PCLKCR1_BITS { /* bits description */
uint16_t EPWM1ENCLK:1; /* 0 Enable SYSCLKOUT to EPWM1 */
uint16_t EPWM2ENCLK:1; /* 1 Enable SYSCLKOUT to EPWM2 */
uint16_t EPWM3ENCLK:1; /* 2 Enable SYSCLKOUT to EPWM3 */
uint16_t EPWM4ENCLK:1; /* 3 Enable SYSCLKOUT to EPWM4 */
uint16_t EPWM5ENCLK:1; /* 4 Enable SYSCLKOUT to EPWM5 */
uint16_t EPWM6ENCLK:1; /* 5 Enable SYSCLKOUT to EPWM6 */
uint16_t rsvd1:2; /* 7:6 reserved */
uint16_t ECAP1ENCLK:1; /* 8 Enable SYSCLKOUT to ECAP1 */
uint16_t ECAP2ENCLK:1; /* 9 Enable SYSCLKOUT to ECAP2 */
uint16_t ECAP3ENCLK:1; /* 10 Enable SYSCLKOUT to ECAP3 */
uint16_t ECAP4ENCLK:1; /* 11 Enable SYSCLKOUT to ECAP4 */
uint16_t ECAP5ENCLK:1; /* 12 Enable SYSCLKOUT to ECAP5 */
uint16_t ECAP6ENCLK:1; /* 13 Enable SYSCLKOUT to ECAP6 */
uint16_t EQEP1ENCLK:1; /* 14 Enable SYSCLKOUT to EQEP1 */
uint16_t EQEP2ENCLK:1; /* 15 Enable SYSCLKOUT to EQEP2 */
};
union PCLKCR1_REG {
uint16_t all;
struct PCLKCR1_BITS bit;
};
/* Peripheral clock control register 2 bit definitions: */
struct PCLKCR3_BITS { /* bits description */
uint16_t rsvd1:8; /* 7:0 reserved */
uint16_t CPUTIMER0ENCLK:1; /* 8 Enable SYSCLKOUT to CPU-Timer 0 */
uint16_t CPUTIMER1ENCLK:1; /* 9 Enable SYSCLKOUT to CPU-Timer 1 */
uint16_t CPUTIMER2ENCLK:1; /* 10 Enable SYSCLKOUT to CPU-Timer 2 */
uint16_t DMAENCLK:1; /* 11 Enable the DMA clock */
uint16_t XINTFENCLK:1; /* 12 Enable SYSCLKOUT to XINTF */
uint16_t GPIOINENCLK:1; /* Enable GPIO input clock */
uint16_t rsvd2:2; /* 15:14 reserved */
};
union PCLKCR3_REG {
uint16_t all;
struct PCLKCR3_BITS bit;
};
/* PLL control register bit definitions: */
struct PLLCR_BITS { /* bits description */
uint16_t DIV:4; /* 3:0 Set clock ratio for the PLL */
uint16_t rsvd1:12; /* 15:4 reserved */
};
union PLLCR_REG {
uint16_t all;
struct PLLCR_BITS bit;
};
/* Low Power Mode 0 control register bit definitions: */
struct LPMCR0_BITS { /* bits description */
uint16_t LPM:2; /* 1:0 Set the low power mode */
uint16_t QUALSTDBY:6; /* 7:2 Qualification */
uint16_t rsvd1:7; /* 14:8 reserved */
uint16_t WDINTE:1; /* 15 Enables WD to wake the device from STANDBY */
};
union LPMCR0_REG {
uint16_t all;
struct LPMCR0_BITS bit;
};
/* Dual-mapping configuration register bit definitions: */
struct MAPCNF_BITS { /* bits description */
uint16_t MAPEPWM:1; /* 0 EPWM dual-map enable */
uint16_t rsvd1:15; /* 15:1 reserved */
};
union MAPCNF_REG {
uint16_t all;
struct MAPCNF_BITS bit;
};
/* SYS_CTRL_REGS */
#ifdef __cplusplus
#pragma DATA_SECTION("SysCtrlRegsFile")
#else
#pragma DATA_SECTION(SysCtrlRegs,"SysCtrlRegsFile");
#endif
struct SYS_CTRL_REGS SysCtrlRegs;
/* END SYS_CTRL_REGS */
/* System Control Register File: */
struct SYS_CTRL_REGS {
uint16_t rsvd1; /* 0 */
union PLLSTS_REG PLLSTS; /* 1 */
uint16_t rsvd2[8]; /* 2-9 */
union HISPCP_REG HISPCP; /* 10: High-speed peripheral clock pre-scaler */
union LOSPCP_REG LOSPCP; /* 11: Low-speed peripheral clock pre-scaler */
union PCLKCR0_REG PCLKCR0; /* 12: Peripheral clock control register */
union PCLKCR1_REG PCLKCR1; /* 13: Peripheral clock control register */
union LPMCR0_REG LPMCR0; /* 14: Low-power mode control register 0 */
uint16_t rsvd3; /* 15: reserved */
union PCLKCR3_REG PCLKCR3; /* 16: Peripheral clock control register */
union PLLCR_REG PLLCR; /* 17: PLL control register */
/* No bit definitions are defined for SCSR because */
/* a read-modify-write instruction can clear the WDOVERRIDE bit */
uint16_t SCSR; /* 18: System control and status register */
uint16_t WDCNTR; /* 19: WD counter register */
uint16_t rsvd4; /* 20 */
uint16_t WDKEY; /* 21: WD reset key register */
uint16_t rsvd5[3]; /* 22-24 */
/* No bit definitions are defined for WDCR because */
/* the proper value must be written to the WDCHK field */
/* whenever writing to this register. */
uint16_t WDCR; /* 25: WD timer control register */
uint16_t rsvd6[4]; /* 26-29 */
union MAPCNF_REG MAPCNF; /* 30: Dual-mapping configuration register */
uint16_t rsvd7[1]; /* 31 */
};
extern struct SYS_CTRL_REGS SysCtrlRegs;
and in my DSP2833x_Headers_nonBIOS.cmd I defined as follow:
MEMORY
{
PAGE 1
...
SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */
...
}
SECTIONS
{
...
/*** Peripheral Frame 2 Register Structures ***/
SysCtrlRegsFile : > SYSTEM, PAGE = 1
...
}
/* End of file*/
I'm sure that the ranges entered above are correct because in debug mode I can visualize every field pointing to the correct address.
However my problem is when I try to change for instance the SysCtrlRegs.WDCR. This register does never change !! Here is the procedure that I follow:
__asm(" EALLOW");
...
...
SysCtrlRegs.WDCR = 0x0068;
...
...
...
__asm(" EALLOW");
I also tried to modify the register's value in debug mode (Code Composer Studio v 8.3.0) but the behaviour is the same.
An other thing that I'm not understanding is that other fields in the structure SysCtrlRegs can be modified without any kind of problem..
Any help would be appreciated.
Sorry for the length of my post and my bad english, but I'm not a native speaker :)
Hoping in any advice, best regards,
Marco.
