Part Number: TMS320F28379D
Tool/software: TI-RTOS
Hi,
I'm trying to make the C2000 Workshop Lab7 to work in the TI-RTOS. I have lab7 working and I have been going through the labs in TI-RTOS workshop as well.
In the lab exercise ADC_A is configured to be triggered by ePWM2-ADCSOCA. This works fine as long as I'm not using the TI-RTOS.
Now, when I go an import the logic to a TI-RTOS environment, the ADC_A is not triggered by this.
In the TI-RTOS project, I leave most of the heavy lifting to the app.cfg . I have a hwi tied to interrupt 32, which should be the ADCA1, and this function is for now, just incrementing a variable to monitor the behaviour. But the variable stays the same.
Int main()
{
Task_Handle task;
Error_Block eb;
// Initialize the GPIO
InitGpio();
InitPeripheralClocks();
// Setup the GPIO for DEVboard LEDs
SetupGpio(conf_TI_EPWM);
InitAdcA();
InitEPwm();
System_printf ("enter main()\n");
Error_init (&eb);
// Create first task
task = Task_create(taskFxn1, NULL, &eb);
if (task == NULL)
{
System_printf ("Task_create() failed!\n");
BIOS_exit(0);
}
// Create second task
task = Task_create(taskFxn2, NULL, &eb);
if (task == NULL)
{
System_printf ("Task_create() failed!\n");
BIOS_exit(0);
}
BIOS_start(); /* does not return */
return(0);
}
void InitAdcA()
{
asm(" EALLOW");
hwiCounter =+ 1;
// Reset the ADC following best practices
DevCfgRegs.SOFTPRES13.bit.ADC_A = 1; // ADC is reset
DevCfgRegs.SOFTPRES13.bit.ADC_A = 0; // ADC is released
// Configure ADC base registers
AdcaRegs.ADCCTL1.all = 0x0004; // Main configuration
// bit 15-14 00: reserved
// bit 13 0: ADCBSY, ADC busy, Read-only
// bit 12 0: reserved
// bit 11-8 000: ADCBSYCHN, ADC busy channel, Read-only
// bit 7 0: ADCPWDNZ, ADC power down, 0 = powered down, 1 = powered up
// bit 6-3 0000: reserved
// bit 2 1: INTPULSEPOS, INT pulse generation, 0 = SOC, 1 = EOC
// bit 1-0 00: reserved
AdcaRegs.ADCCTL2.all = 0x0006; // Clock configuration
// bit 15-8 0's: reserved
// bit 7 0: SIGNALMODE, configured by AdcSetMode()
// below to get calibration correct
// bit 6 0: RESOLUTION, configured by AdcSetMode()
// below to get calibration correct
// bit 5-4 00: reserved
// bit 3-0 0110: PRESCALE, ADC clock prescaler. 0110=CPUCLK/4
AdcaRegs.ADCBURSTCTL.all = 0x0000;
// bit 15 0: BURSTEN, 0=burst mode disabled, 1=burst mode enabled
// bit 14-12 000: reserved
// bit 11-8 0000: BURSTSIZE, 0=1 SOC converted (don't care)
// bit 7-6 00: reserved
// bit 5-0 000000: BURSTTRIGSEL, 00=software only (don't care)
// Configure resolution and signal mode
// Perform calibration from OTP for the configured mode
AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
// Configure SOC-0
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 7; // Trigger using ePWM2-ADCSOCA
AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0; // Convert channel ADCINA0 (Ch. 0)
AdcaRegs.ADCSOC0CTL.bit.ACQPS = 19; // Acquisition window, 19+1 cycles
AdcaRegs.ADCINTSOCSEL1.bit.SOC0 = 0; // ADC does not trigger SOC
AdcaRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 0; // All SOC are equal
// Configure ADCA1 interrupt
AdcaRegs.ADCINTSEL1N2.bit.INT1CONT = 1; // Interrupt pulses regardless of state
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; // Enable the interrupt in the ADC
AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 0; // EOC0 triggers interrupt
// Interrupt enable is disabled because the file is made for TI-RTOS which
// will handle the interrupts in the configuration file
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1; // Power up the ADC
DELAY_US(1000);
asm(" EDIS");
}
void InitEPwm(void)
{
EALLOW;
// Maximum input clock for ePWM is 100MHz
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 1; // Divide PLLSYSCLK by 2
// Must disable the clock to the ePWM to synchronize the outputs
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
/**
* *************
* Set ePWM2 to trigger ADC SOC-A at a 16 kHz rate
* *************
*/
EALLOW;
DevCfgRegs.SOFTPRES2.bit.EPWM2 = 1; // Device is in reset
DevCfgRegs.SOFTPRES2.bit.EPWM2 = 0; // Device is release
EDIS;
EPwm2Regs.TBCTL.bit.CTRMODE = 0x3; // Disable timer
EPwm2Regs.TBCTL.all = 0xC033; // Configure ePWM2 timer
// bit 15-14 11: FREE/SOFT, 11 = ignore emulation suspend
// bit 13 0: PHSDIR, 0 = count down after sync event
// bit 12-10 000: CLKDIV, 000 => TBCLK = HSPCLK/1
// bit 9-7 000: HSPCLKDIV, 000 => HSPCLK = EPWMCLK/1
// bit 6 0: SWFSYNC, 0 = no software sync produced
// bit 5-4 11: SYNCOSEL, 11 = sync-out disabled
// bit 3 0: PRDLD, 0 = reload PRD on counter=0
// bit 2 0: PHSEN, 0 = phase control disabled
// bit 1-0 11: CTRMODE, 11 = timer stopped (disabled)
EPwm2Regs.TBCTR = 0x0000; // Clear timer counter
EPwm2Regs.TBPRD = 1999; // 16kHz sampling with 100MHz clock
EPwm2Regs.TBPHS.bit.TBPHS = 0x0000; // Set timer phase
EPwm2Regs.ETPS.all = 0x0100; // Configure SOC-A
// bit 15-14 00: EPWMxSOCB, read-only
// bit 13-12 00: SOCBPRD, don't care
// bit 11-10 00: EPWMxSOCA, read-only
// bit 9-8 01: SOCAPRD, 01 = generate SOCA on first event
// bit 7-4 0000: reserved
// bit 3-2 00: INTCNT, don't care
// bit 1-0 00: INTPRD, don't care
EPwm2Regs.ETSEL.all = 0x0A00; // Enable SOCA to ADC
// bit 15 0: SOCBEN, 0 = disable SOCB
// bit 14-12 000: SOCBSEL, don't care
// bit 11 1: SOCAEN, 1 = enable SOCA
// bit 10-8 010: SOCASEL, 010 = SOCA on PRD event
// bit 7-4 0000: reserved
// bit 3 0: INTEN, 0 = disable interrupt
// bit 2-0 000: INTSEL, don't care
EPwm2Regs.TBCTL.bit.CTRMODE = 0x0; // Enable timer
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; // TBCLK to ePWM modules enabled
EDIS;
}
Any help is appreciated, I have been stuck on this one for quite a while.
Best regards,
Tero
