CCS/TMS320F28069M: Creation three pwm signals .

Tool/software: Code Composer Studio

Hello everyone! I am beginner in this work with microconrollers and I really need your help. I have some problem with microconroller TMS320 980 F28069MPZT CB-6CA77TM on the TAPAS board.

The Goal:
Right now my purpose is created three pwm signals with some dead-time and phase shift. I use RAM memory for initialization of the program.

The Problem:
Then only one signal is created it works fine if:

EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active high complementary
or
EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_LOW; // Active low complementary

However, if I use (EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HI;) or if I don't even use the POLSEL command then the loop stops in the main after couple of thousand of times

If the "pause" button would be clicked during the stuck, then the error appears: "Break at address "0x3ff671" with no debug information available, or outside of program code."

If I add at least one pwm with phase shift then the same error appears again. Even if, I don't use dead-time at all.

The Question:

I think it is problem with memory, but I can not say that is exact problem. Maybe do you have some thoughts about it?

The Remark:

In future, I will add an interrupt method to create a sinusoidal pwm signal, but it takes much hugher memory. I tried to use at least for one pwm but it works for couple seconds ( I see the correct curve in oscilloscope) and then the same error is appeared.

Thank you for attention!

The Code:

#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
#include "IQmathLib.h"
#include "math.h"

void InitEPwmTimer(void);

// Global variables used in this example
Uint16 PRD = 2252; //PWM Period 2252
int loop_count = 0;
int int_count = 0;

void main()
{

// Step 1. Initialize System Control:
InitSysCtrl();

// Step 2. Initialize GPIO:
InitGpio();
InitEPwmGpio();

// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;

// Initialize the PIE control registers to their default state.
InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;

// Initialize the PIE vector table with pointers to the shell Interrupt
InitPieVectTable();

// Step 4. Initialize all the Device Peripherals:
InitEPwmTimer(); // For this example, only initialize the ePWM Timer

// Initialize counters:
// Enable CPU INT3 which is connected to EPWM1-6 INT:
IER |= M_INT3;

// Enable EPWM INTn in the PIE: Group 3 interrupt 1-6
PieCtrlRegs.PIEIER3.bit.INTx4 = 1;

// Enable global Interrupts and higher priority real-time debug events:
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM

// Step 6. IDLE loop. Just sit and loop forever (optional):
while(1){
loop_count++;
}

} // End main

void InitEPwmTimer()
{

EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Stop all the TB clocks
EDIS;

// Enable Sync

EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Pass through
EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm4Regs.TBCTL.bit.FREE_SOFT = 0; // Initially disable Free/Soft
EPwm4Regs.TBPRD = PRD-1; // Set up PWM1 Period
EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up mode
EPwm4Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm4Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm4Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
EPwm4Regs.TBCTR = 0x0000; // Clear timer counter
EPwm4Regs.CMPA.half.CMPA = PRD/2; //CompareA event at half of PRD
EPwm4Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Master module
EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm4Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count
EPwm4Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A, down count
EPwm4Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM1B on event B, up count
EPwm4Regs.AQCTLB.bit.CAD = AQ_SET; // Clear PWM1B on event B, down
//Dead-base
EPwm4Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active high complementary
EPwm4Regs.DBRED = 15;
EPwm4Regs.DBFED = 15;

// ePWM2
EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Pass through
EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm5Regs.TBCTL.bit.FREE_SOFT = 0; // Initially disable Free/Soft Bits
EPwm5Regs.TBPRD = PRD-1; // Set up PWM1 Period
EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up mode
EPwm5Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm5Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm5Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
EPwm5Regs.TBCTR = 0x0000; // Clear timer counter
EPwm5Regs.CMPA.half.CMPA = PRD/2; //CompareA event at half of period
EPwm5Regs.TBPHS.half.TBPHS = 750; // Set Phase register to zero
EPwm5Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
EPwm5Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm5Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm5Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm5Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm5Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm5Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count
EPwm5Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A, down count
EPwm5Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM1B on event B, up count
EPwm5Regs.AQCTLB.bit.CAD = AQ_SET; // Clear PWM1B on event B, down
//Dead-base
EPwm5Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm5Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active high complementary
EPwm5Regs.DBRED = 15;
EPwm5Regs.DBFED = 15;

// The EPwm6 is the same like EPwm5 but with different PHSEN

EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Start all the timers synced
EDIS;
}