TMS320F28335: About clock design.

Hello Lian,

There are two different specs here.  First is with PLL disabled, second is with PLL enabled.  Also, we need to differentiate between using a crystal, and providing an actual clock signal.

With the PLL disabled, you can provide a XCLKIN signal between 4 and 150 MHz to the device.  With the PLL enabled, XCLKIN signal can be 33.3 to 200 ns (5 to 30 MHz).  However, crystals are further limited to between 20 and 35 MHz.  So, with the PLL enabled, we should choose a crystal between 20 and 30 MHz).

What most people do is use a 30 MHz crystal and use the PLL to multiply up by 10/2 (i.e. 5).  This gives 150 MHz.  Note that maximum PLL factor is 5 on this device, so really to hit 150 MHz operation you have to use a 30 MHz crystal.

Finally, the Table numbers in your pictures don't line up with the current datasheet, sprs439n.  Please make sure you are using the latest/correct datasheet for the device.

Regards,

David

Thanks David,
I had a draft typed up almost verbatim!

One additional note to add - If you are using a single ended clock on X1, it must be a 1.9 V . If you are using XCLKIN, it is a 3.3 V Clock.
This is documented in the "Signal Descriptions Table" as well as the "OSC and PLL Block" Section.

Here is a persistent link to always serve the latest datasheet version : www.ti.com/.../tms320f28335

Thanks,
Mark