CCS/LAUNCHXL-F28379D: Multiple ISR causing problems

Hi Ashima,

This means that the declaration of "interrupt void ADCB1_ISR(void)" was done twice.  Somehwere in your code, you are defining this again.  Make sure that this is interrupt routine is defined only once.

Regards,

Joseph

Hi Joseph,
I have mentioned the ISR only once in my code. Please check if it is wrong. I am attaching the code.

//###########################################################################
//
// FILE: adc_soc_epwm_cpu01.c
//
// TITLE: ADC triggering via epwm for F2837xS.
//
//! \addtogroup cpu01_example_list
//! <h1> ADC ePWM Triggering (adc_soc_epwm)</h1>
//!
//! This example sets up the ePWM to periodically trigger the ADC.
//!
//! After the program runs, the memory will contain:\n
//! - \b AdcaResults \b: A sequence of analog-to-digital conversion samples from
//! pin A0. The time between samples is determined based on the period
//! of the ePWM timer.
//
//###########################################################################
// $TI Release: F2837xS Support Library v210 $
// $Release Date: Tue Nov 1 15:35:23 CDT 2016 $
// $Copyright: Copyright (C) 2014-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################

//
// Included Files
//
#include "F28x_Project.h"



// Function Prototypes
//
void ConfigureADC(void);
void ConfigureEPWM(void);
void SetupADCEpwm(Uint16 channel);
interrupt void ADCA1_ISR(void);
interrupt void ADCB1_ISR(void);


//
// Defines
//
#define FL 65536
#define z11 5
#define z12 3
#define p11 8.3
#define Kp1 8854
#define z21 666
#define z22 858
#define p21 88
#define Kp2 8888
#define z31 33
#define z32 8
#define p31 7
#define Kp3 1287
#define z41 56
#define z42 33
#define p41 -3.3
#define Kp4 75
#define tb1 2500
#define tb2 2000
#define tb3 500
#define l 0.00000001

#define bum 0.000001

//
// Globals
//
//Uint16 AdcaResults[RESULTS_BUFFER_SIZE];
//Uint16 resultsIndex;
float a;
float b;
float Err12;
float Err10;
float Err11;
float Err22;
float Err20;
float Err21;
float Err42;
float Err40;
float Err41;
float Dn10;
float Dn11;
float Dn12;
float Dn20=0;
float Dn21;
float Dn22;
float Dn30=0;
float Dn31;
float Dn32;
float Dn40=0;
float Dn41;
float Dn42;
float Dnf3;
float Dnf4;
float Dnf5;
float Iaf;
float Iaf1;
float Ia;
float Ia1;
float IVa;
float IVd;
float IVp;
float IVn;
float Idc;
float Id;
float Va1;
float Vdp;
float Vdn;
float Vpv;
float Vpv1;
float Idp;
float Idn;
float Va2;
float Vd1;
float Va4;
float Vd4;
float c;
float e;
float Vd2;
float Ppv;
float Ppv1;
float Pa1;
float Dnf1;
float Dnf2;
float Dn;
float Dn1;
float Vsref=10;
float Vsref1;
float Pp;
float Pd;
float Vd;
float f;
float f1;
float Vaf10;
float Va10;
float Va11;
float Va12;
float Va13;
float Va14;
float Va15;
float Va16;
float Vad1;
float Va17;
float Va18;
float Va19;
float Va110;
float Va111;
float Va112;
float Va113;
float Va114;
float Va115;
float Va116;
float Va117;
float Va118;
float Vaf20;
float Va20;
float Va21;
float Va22;
float Va23;
float Va24;
float Va25;
float Va26;
float Vad1;
float Va27;
float Va28;
float Va29;
float Va210;
float Va211;
float Va212;
float Va213;
float Va214;
float Va215;
float Va216;
float Va217;
float Va218;

Uint16 CMPduty1;
Uint16 CMPduty2;
Uint16 CMPduty3;
Uint16 CMPduty4;
Uint16 CMPduty5;
Uint16 n;

interrupt void ADCA1_ISR(void)

{
do{
// if(AdccRegs.ADCINTFLG.bit.ADCINT1==1)
// {
Err12=Err11;
Err11=Err10;
Dn12=Dn11;
Dn11=Dnf1;
Vd1=AdcaResultRegs.ADCRESULT0;
Va10=165*((2*Vd1/65536)-1);

Va118=Va117;
Va117=Va116;
Va116=Va115;
Va115=Va114;
Va114=Va113;
Va113=Va112;
Va112=Va111;
Va111=Va110;
Va110=Va19;
Va19=Va18;
Va18=Va17;
Va17=Va16;
Va16=Va15;
Va15=Va14;
Va14=Va13;
Va13=Va12;
Va12=Va11;
Va11=Va10;
Vaf10=(Va10+Va11+Va12+Va13+Va14+Va15+Va16+Va17+Va18+Va19+Va110+Va111+Va112+Va113+Va114+Va115+Va116+Va117+Va118)/19;
// Vaf10=(l)*(0.08*Va10+0.484*Va11+1.201*Va12+1.6*Va13+1.201*Va14+0.484*Va15+0.08*Va16)+5.634*Vaf11-13.23*Vaf12+4.381*Vaf15+16.56*Vaf13-11.66*Vaf14-0.6857*Vaf16;

Err10=30-Vaf10;
Dn10=(p11+1)*Dn11-(p11*Dn12)+(Kp1*Err10)-(Kp1*(z11+z12)*Err11)+(Kp1*z11*z12*Err12);
if(Dn10>0.8)
{
Dnf1=0.8;
}
else if(Dn10<0.15)
{
Dnf1=0.15;
}
else
{
Dnf1=Dn10;
}
CMPduty1=(tb1*0.5);
EPwm2Regs.CMPA.bit.CMPA = CMPduty1;
// }


AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Must acknowledge the PIE group

// PieCtrlRegs.PIEACK.all = 0xFFFF;
// PieCtrlRegs.PIEIFR1.bit.INTx1=0;
// PieCtrlRegs.PIEIER1.bit.INTx1 = 1;

// DINT;
}while(1);
}
interrupt void ADCB1_ISR(void)

{
// EINT;
do{
// if(AdcbRegs.ADCINTFLG.bit.ADCINT1==1)
// {
Ppv1=Ppv;
Vpv1=Vpv;
Ia1=Ia;Vsref1=Vsref;
for (n=0; n<60000; n++)
{}
Vd2=AdcbResultRegs.ADCRESULT0;
Vpv=165*((2*Vd2/65536)-1);
Idc=AdcbResultRegs.ADCRESULT1;
Ia=15*((2*Idc/65536)-1);


// AdcbRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag

// PieCtrlRegs.PIEACK.all = 0xFFFF;
// PieCtrlRegs.PIEIFR2.bit.INTx2=0;
// PieCtrlRegs.PIEIER2.bit.INTx2 = 1;

DINT;
}while(1);
}



//volatile Uint16 bufferFull;
//
void main(void)

{
//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xS_SysCtrl.c file.
//
InitSysCtrl();

//

InitGpio(); // Skipped for this example


InitPieCtrl();

//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
IER = 0x0000;
IFR = 0x0000;


InitPieVectTable();
EALLOW;
// ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL=0;
CpuSysRegs.PCLKCR2.bit.EPWM1=1;
CpuSysRegs.PCLKCR2.bit.EPWM2=1;
CpuSysRegs.PCLKCR2.bit.EPWM6=1;
CpuSysRegs.PCLKCR2.bit.EPWM3=1;
CpuSysRegs.PCLKCR2.bit.EPWM7=1;
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV=1;
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=1;
ClkCfgRegs.SYSPLLMULT.bit.FMULT=0;
ClkCfgRegs.SYSPLLMULT.bit.IMULT=40;

EDIS;


// Configure the ADC and power it up
//
ConfigureADC();

//
// Configure the ePWM
//
ConfigureEPWM();
// Interrupt where we will change the Compare Values
//
EALLOW;
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = 1; // Generate INT on 3rd event
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = 1; // Generate INT on 3rd event
EPwm6Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm6Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm6Regs.ETPS.bit.INTPRD = 1; // Generate INT on 3rd event
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = 1; // Generate INT on 3rd event
EPwm7Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm7Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm7Regs.ETPS.bit.INTPRD = 1; // Generate INT on 3rd event

EDIS;
//
// Setup the ADC for ePWM triggered conversions on channel 0
//
SetupADCEpwm(0);

EALLOW;

//
// Disable internal pull-up for the selected output pins
// for reduced power consumption
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
//
GpioCtrlRegs.GPAPUD.bit.GPIO0 = 1; // Disable pull-up on GPIO2 (EPWM2A)
GpioCtrlRegs.GPAPUD.bit.GPIO1 = 1; // Disable pull-up on GPIO2 (EPWM2A)
GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1; // Disable pull-up on GPIO2 (EPWM2A)
GpioCtrlRegs.GPAPUD.bit.GPIO3 = 1; // Disable pull-up on GPIO3 (EPWM2B)
GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1; // Disable pull-up on GPIO3 (EPWM2B)
GpioCtrlRegs.GPAPUD.bit.GPIO4 = 1; // Disable pull-up on GPIO3 (EPWM2B)
GpioCtrlRegs.GPAPUD.bit.GPIO11 = 1; // Disable pull-up on GPIO3 (EPWM2B)

//
// Configure EPwm-2 pins using GPIO regs
// This specifies which of the possible GPIO pins will be EPWM2 functional pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO2 as EPWM2A
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // Configure GPIO3 as EPWM2B
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // Configure GPIO2 as EPWM2A
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // Configure GPIO3 as EPWM2B
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO3 as EPWM2B
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // Configure GPIO3 as EPWM2B
GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO3 as EPWM2B

EDIS;

// enable PIE interrupt
//
EALLOW;
PieCtrlRegs.PIEIER1.bit.INTx1 = 1;
PieCtrlRegs.PIEIER1.bit.INTx2 = 1;
PieVectTable.ADCA1_INT = &ADCA1_ISR ; //function for ADCA interrupt 1
PieVectTable.ADCB1_INT = &ADCB1_ISR; //function for ADCB interrupt 1
// AdcbRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
// PieCtrlRegs.PIEIFR1.bit.INTx2=0;
IER |= 0x0001; // Enable CPU INT1 for ADCINT1,ADCINT2,ADCINT9,TripZone
IER |= 0x0002; // CPU timer 2 is connected to CPU INT 14
EINT;
// Enable Global interrupt INTM
ERTM;
// Enable Global realtime interrupt DBGM
// sync ePWM
EDIS;
//
//
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;


//start ePWM
//
EPwm1Regs.ETSEL.bit.SOCAEN = 1; //enable SOCA
EPwm1Regs.ETSEL.bit.SOCBEN = 1; //enable SOCA
EPwm1Regs.TBCTL.bit.CTRMODE = 0; //unfreeze, and enter up count mode
EPwm2Regs.ETSEL.bit.SOCAEN = 1; //enable SOCA
EPwm2Regs.ETSEL.bit.SOCBEN = 1; //enable SOCB
EPwm2Regs.TBCTL.bit.CTRMODE = 0; //unfreeze, and enter up count mode
EPwm6Regs.ETSEL.bit.SOCAEN = 1; //enable SOCA
EPwm6Regs.ETSEL.bit.SOCBEN = 1; //enable SOCA
EPwm6Regs.TBCTL.bit.CTRMODE = 0; //unfreeze, and enter up count mode
EPwm7Regs.ETSEL.bit.SOCAEN = 1; //enable SOCA
EPwm7Regs.ETSEL.bit.SOCBEN = 1; //enable SOCA
EPwm7Regs.TBCTL.bit.CTRMODE = 0; //unfreeze, and enter up count mode
EPwm3Regs.ETSEL.bit.SOCAEN = 1; //enable SOCA
EPwm3Regs.TBCTL.bit.CTRMODE = 0; //unfreeze, and enter up count mode
EPwm3Regs.TBCTL.bit.HSPCLKDIV = 100; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = 100;


EDIS;

do
{
EALLOW;
DINT;

//
IER |= M_INT1; //Enable group 1 interrupts
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
//
// }
EDIS;
// for (n=1 ; n<100 ; n++)
//{}

} while(1);
}

// ConfigureADC - Write ADC configurations and power up the ADC for both
// ADC A and ADC B
//
void ConfigureADC(void)
{
EALLOW;
//write configurations
//
AdcaRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to 200MHz/1
AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
//Set pulse positions to late
//
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;
//power up the ADC
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;

AdcbRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to 200MHz/1
AdcSetMode(ADC_ADCB, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;
//delay for 1ms to allow ADC time to power up
AdccRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to 200MHz/1
AdcSetMode(ADC_ADCC, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
//Set pulse positions to late
//
AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1;
//power up the ADC
AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1;

AdcdRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to 200MHz/1
AdcSetMode(ADC_ADCD, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
//Set pulse positions to late
//
AdcdRegs.ADCCTL1.bit.INTPULSEPOS = 1;
//power up the ADC
AdcdRegs.ADCCTL1.bit.ADCPWDNZ = 1;

//
// DELAY_US(1000);

EDIS;
}

//
// ConfigureEPWM - Configure EPWM SOC and compare values
//
void ConfigureEPWM(void)
{
EALLOW;
// EPWM2A TRIGGERING FOR PWM
// Assumes ePWM clock is already enabled
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC when CMPA equal to TBPRD
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
// Set compare A value to 2048 counts
EPwm1Regs.TBPRD = tb3; // Set period to 65536 counts
EPwm1Regs.TBCTL.bit.CTRMODE = 0; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = 0;
// Set actions
EPwm1Regs.AQCTLA.bit.PRD = AQ_CLEAR; // Clear PWM2A on Period
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on event A,


EPwm1Regs.ETSEL.bit.SOCBEN = 1; // Enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCBSEL = 4; // Select SOC when CMPA equal to TBPRD
EPwm1Regs.ETPS.bit.SOCBPRD = 1; // Generate pulse on 1st event
// Set compare A value to 2048 counts
EPwm1Regs.TBPRD = tb3; // Set period to 65536 counts
EPwm1Regs.TBCTL.bit.CTRMODE = 0; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = 0;
// Set actions
EPwm1Regs.AQCTLB.bit.PRD = AQ_CLEAR; // Clear PWM2A on Period
EPwm1Regs.AQCTLB.bit.CBU = AQ_SET; // Set PWM2A on event A,
// EPwm1Regs.CMPB.bit.CMPB = 1000*0.5;
// Interrupt where we will change the Compare Values
EPwm1Regs.ETSEL.bit.INTSEL = 4; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = 01; // Generate INT on every event // up count

// Interrupt where we will change the Compare Values
EPwm2Regs.ETSEL.bit.INTSEL = 4; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = 01; // Generate INT on every event // up count

EPwm2Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm2Regs.ETSEL.bit.SOCASEL = 4; // Select SOC when CMPA equal to TBPRD
EPwm2Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
// Set compare A value to 2048 counts
EPwm2Regs.TBPRD = tb1; // Set period to 65536 counts
EPwm1Regs.CMPA.bit.CMPA = tb3*0.5;
EPwm2Regs.TBCTL.bit.CTRMODE = 0; // Count up
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm2Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = 0;
// Set actions
EPwm2Regs.AQCTLA.bit.PRD = AQ_CLEAR; // Clear PWM2A on Period
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on event A,

// Interrupt where we will change the Compare Values
EPwm2Regs.ETSEL.bit.INTSEL = 4; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = 01; // Generate INT on every event // up count

// Assumes ePWM clock is already enabled
EPwm2Regs.ETSEL.bit.SOCBEN = 1; // Enable SOC on A group
EPwm2Regs.ETSEL.bit.SOCBSEL = 4; // Select SOC when CMPA equal to TBPRD
EPwm2Regs.ETPS.bit.SOCBPRD = 1; // Generate pulse on 1st event
// Set compare A value to 2048 counts
EPwm2Regs.TBPRD = tb1; // Set period to 65536 counts
EPwm2Regs.TBCTL.bit.CTRMODE = 0; // Count up
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm2Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = 0;
// Set actions
EPwm2Regs.AQCTLB.bit.PRD = AQ_CLEAR; // Clear PWM2A on Period
EPwm2Regs.AQCTLB.bit.CBU = AQ_SET; // Set PWM2A on event A,
EPwm2Regs.CMPB.bit.CMPB = tb1*0.3;
// Interrupt where we will change the Compare Values
EPwm2Regs.ETSEL.bit.INTSEL = 4; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = 01; // Generate INT on every event // up count

// EPWM6A TRIGGERING FOR PWM
// Assumes ePWM clock is already enabled
EPwm6Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm6Regs.ETSEL.bit.SOCASEL = 4; // Select SOC when CMPA equal to TBPRD
EPwm6Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
// Set compare A value to 2048 counts
EPwm6Regs.TBPRD = tb2; // Set period to 65536 counts
// EPwm6Regs.CMPA.bit.CMPA = 0.49*99;
EPwm6Regs.TBCTL.bit.CTRMODE = 0; // Count up
EPwm6Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm6Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm6Regs.TBCTR = 0x0000; // Clear counter
EPwm6Regs.TBCTL.bit.HSPCLKDIV = 0; // Clock ratio to SYSCLKOUT
EPwm6Regs.TBCTL.bit.CLKDIV = 0;
// Set actions

EPwm6Regs.AQCTLA.bit.PRD = AQ_CLEAR; // Clear PWM2A on Period
EPwm6Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on event A,
// Set PWM2A on event A,

// Interrupt where we will change the Compare Values
//
EPwm6Regs.ETSEL.bit.INTSEL = 4; // Select INT on Zero event
EPwm6Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm6Regs.ETPS.bit.INTPRD = 01; // Generate INT on every event // up count
//EPWM6B FOR PWM
// EPwm6Regs.CMPB.bit.CMPB =0.7*1000;
EPwm6Regs.ETSEL.bit.SOCBEN = 1; // Enable SOC on A group
EPwm6Regs.ETSEL.bit.SOCBSEL = 5; // Select SOC when CMPA equal to TBPRD
EPwm6Regs.ETPS.bit.SOCBPRD = 1; // Generate pulse on 1st event
// Set compare A value to 2048 counts
EPwm6Regs.TBPRD = tb2; // Set period to 65536 counts
EPwm6Regs.TBCTL.bit.CTRMODE = 0; // Count up
EPwm6Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm6Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm6Regs.TBCTR = 0x0000; // Clear counter
EPwm6Regs.TBCTL.bit.HSPCLKDIV = 0; // Clock ratio to SYSCLKOUT
EPwm6Regs.TBCTL.bit.CLKDIV = 0;
// Set actions

EPwm6Regs.AQCTLB.bit.PRD = 1; // Clear PWM2A on Period
EPwm6Regs.AQCTLB.bit.CBU = 2; // Set PWM2A on event A,

// Interrupt where we will change the Compare Values
//
EPwm6Regs.ETSEL.bit.INTSEL = 4; // Select INT on Zero event
EPwm6Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm6Regs.ETPS.bit.INTPRD = 01; // Generate INT on every event // up count


//EPWM3 TRIGGERING FOR ADC TRIGGERING
EPwm3Regs.ETSEL.bit.SOCAEN= 1; // Enable SOC on A group
EPwm3Regs.ETSEL.bit.SOCASEL= 4; // Select SOC when CMPA equal to TBPRD
EPwm3Regs.ETPS.bit.SOCAPRD= 1; // Generate pulse on 1st event
// Set compare A value to 2048 counts
EPwm3Regs.CMPA.bit.CMPA =0.5412*5000;
EPwm3Regs.TBPRD =5000; // Set period to 65536 counts
EPwm3Regs.TBCTL.bit.CTRMODE = 0; // up counter

EPwm3Regs.TBCTL.bit.CTRMODE = 0; // Count up
EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm3Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm3Regs.TBCTR = 0x0000; // Clear counter
EPwm3Regs.AQCTLA.bit.PRD = AQ_CLEAR; // Clear PWM2A on Period
EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on event A,
EPwm3Regs.ETSEL.bit.INTSEL = 4; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = 01;
//EPWM7 TRIGGERING FOR ADC TRIGGERING of BDC
EPwm7Regs.ETSEL.bit.SOCAEN= 1; // Enable SOC on A group
EPwm7Regs.ETSEL.bit.SOCASEL= 4; // Select SOC when CMPA equal to TBPRD
EPwm7Regs.ETPS.bit.SOCAPRD= 1; // Generate pulse on 1st event
// Set compare A value to 2048 counts
EPwm7Regs.CMPA.bit.CMPA =0.3*tb2;
EPwm7Regs.TBPRD =tb2; // Set period to 65536 counts
EPwm7Regs.TBCTL.bit.CTRMODE = 0; // up counter

EPwm7Regs.TBCTL.bit.CTRMODE = 0; // Count up
EPwm7Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm7Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm7Regs.TBCTR = 0x0000; // Clear counter
EPwm7Regs.AQCTLA.bit.PRD = AQ_CLEAR; // Clear PWM2A on Period
EPwm7Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on event A,
EPwm7Regs.ETSEL.bit.INTSEL = 4; // Select INT on Zero event
EPwm7Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm7Regs.ETPS.bit.INTPRD = 01;

EDIS;
}


// SetupADCEpwm - Setup ADC EPWM acquisition window
//
void SetupADCEpwm(Uint16 channel)
{
EALLOW;
//ADC_A for voltage controlling
AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0; //SOC0 will convert pin A0 70 and A1 30
AdcaRegs.ADCSOC0CTL.bit.ACQPS = 79; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 8; //trigger on ePWM2 B SOCA/C
AdcaRegs.ADCINTSEL1N2.bit.INT2SEL = 0; //end of SOC1 will set INT1 flag
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; //enable INT2 flag
// AdcaRegs.ADCINTFLGCLR.bit.ADCINT2 = 1; //make sure INT2 flag is cleared
AdcaRegs.ADCINTSEL1N2.bit.INT1CONT = 1;


//ADC_A for voltage controlling
AdcaRegs.ADCSOC1CTL.bit.CHSEL = 2; //SOC1 will convert pin A2 29 and A3 26
AdcaRegs.ADCSOC1CTL.bit.ACQPS = 79; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = 5; //trigger on ePWM2 B SOCA/C
AdcaRegs.ADCINTSEL1N2.bit.INT2SEL = 0; //end of SOC1 will set INT1 flag
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; //enable INT2 flag
// AdcaRegs.ADCINTFLGCLR.bit.ADCINT2 = 1; //make sure INT2 flag is cleared
AdcaRegs.ADCINTSEL1N2.bit.INT1CONT = 1;
// AdcaRegs.ADCINTFLG.bit.ADCINT1 = 1;

//ADC_A for voltage controlling
AdcaRegs.ADCSOC2CTL.bit.CHSEL = 4; //SOC0 will convert pin A0 70 and A1 30
AdcaRegs.ADCSOC2CTL.bit.ACQPS = 79; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC2CTL.bit.TRIGSEL = 5; //trigger on ePWM2 B SOCA/C
AdcaRegs.ADCINTSEL1N2.bit.INT2SEL = 0; //end of SOC1 will set INT1 flag
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; //enable INT2 flag
// AdcaRegs.ADCINTFLGCLR.bit.ADCINT2 = 1; //make sure INT2 flag is cleared
AdcaRegs.ADCINTSEL1N2.bit.INT1CONT = 1;


// ADC_B for MPPT FOR V_PV
AdcbRegs.ADCSOC0CTL.bit.CHSEL = 2; //SOC0 will convert pin A2 and A3
AdcbRegs.ADCSOC0CTL.bit.ACQPS = 79; //sample window is 100 SYSCLK cycles
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = 9; //trigger on ePWM2 SOCA/C
AdcbRegs.ADCINTSEL1N2.bit.INT1SEL = 0; //end of SOC0 will set INT1 flag
AdcbRegs.ADCINTSEL1N2.bit.INT1E = 1; //enable INT1 flag
// AdcbRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared
AdcbRegs.ADCINTSEL1N2.bit.INT1CONT = 1;
// AdcbRegs.ADCINTFLG.bit.ADCINT1 = 1;
// FOR I_PV
AdcbRegs.ADCSOC1CTL.bit.CHSEL = 4; //SOC1 will convert pin A2 and A3
AdcbRegs.ADCSOC1CTL.bit.ACQPS = 79; //sample window is 100 SYSCLK cycles
AdcbRegs.ADCSOC1CTL.bit.TRIGSEL = 9; //trigger on ePWM2 SOCA/C
AdcbRegs.ADCINTSEL1N2.bit.INT2SEL = 4; //end of SOC1 will set INT1 flag
AdcbRegs.ADCINTSEL1N2.bit.INT2E = 1; //enable INT2 flag
// AdcbRegs.ADCINTFLGCLR.bit.ADCINT2 = 1; //make sure INT2 flag is cleared

AdcbRegs.ADCSOC1CTL.bit.CHSEL = 4; //SOC1 will convert pin A2 and A3
AdcbRegs.ADCSOC1CTL.bit.ACQPS = 79; //sample window is 100 SYSCLK cycles
AdcbRegs.ADCSOC1CTL.bit.TRIGSEL = 9; //trigger on ePWM2 SOCA/C
AdcbRegs.ADCINTSEL1N2.bit.INT2SEL = 4; //end of SOC1 will set INT1 flag
AdcbRegs.ADCINTSEL1N2.bit.INT2E = 1; //enable INT2 flag
// AdcbRegs.ADCINTFLGCLR.bit.ADCINT2 = 1; //make sure INT2 flag is cleared

// AdcbRegs.ADCINTFLG.bit.ADCINT1 = 1;
// FOR I_PV
AdccRegs.ADCSOC1CTL.bit.CHSEL = 4; //SOC1 will convert pin A2 and A3
AdccRegs.ADCSOC1CTL.bit.ACQPS = 79; //sample window is 100 SYSCLK cycles
AdccRegs.ADCSOC1CTL.bit.TRIGSEL = 8; //trigger on ePWM2 SOCA/C
AdccRegs.ADCINTSEL1N2.bit.INT2SEL = 4; //end of SOC1 will set INT1 flag
AdccRegs.ADCINTSEL1N2.bit.INT2E = 1; //enable INT2 flag
// AdcbRegs.ADCINTFLGCLR.bit.ADCINT2 = 1; //make sure INT2 flag is cleared

AdcdRegs.ADCSOC1CTL.bit.CHSEL = 4; //SOC1 will convert pin A2 and A3
AdcdRegs.ADCSOC1CTL.bit.ACQPS = 79; //sample window is 100 SYSCLK cycles
AdcdRegs.ADCSOC1CTL.bit.TRIGSEL = 11; //trigger on ePWM7 SOCA/C
AdcdRegs.ADCINTSEL1N2.bit.INT2SEL = 4; //end of SOC1 will set INT1 flag
AdcdRegs.ADCINTSEL1N2.bit.INT2E = 1; //enable INT2 flag
// AdcbRegs.ADCINTFLGCLR.bit.ADCINT2 = 1; //make sure INT2 flag is cleared

EDIS;
}




// End of file
//

Hi Ashima,

Try removing these declarations at the start of adc_soc_epwm_cpu01.c:

interrupt void ADCA1_ISR(void);
interrupt void ADCB1_ISR(void);

These are already defined in other externally included files.

Regards,
Joseph

I tried it but same error was shown.

Thank you Joseph. That helped me a lot.