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TMS320F28335: TMS320F28335 CAN receive interruption

Part Number: TMS320F28335


Hi,

When debugging with CAN box, it needs to send data 3 times before entering CAN interruption. What's the problem? When sending data for the first and second time, CANMDL and CANMDH values remain unchanged, but changed when for the third time. What is the cause?

 

There is failure of CAN interruption occasionally. According to the check of CANRMP, I found that it had been set to 1 and had not been reset to 0, so the interruption of gif failed and the interruption function failed. But I was really confused. In the interruption function, I judged the receive mailbox according to the bit of rmp and accepted the corresponding data, after that, I reset the corresponding rmp to 0. Theoretically there should be no RMP not reset to 0.

  • When debugging with CAN box, it needs to send data 3 times before entering CAN interruption. What's the problem? When sending data for the first and second time, CANMDL and CANMDH values remain unchanged, but changed when for the third time. What is the cause?

    Is this behavior reproducible every time? Or does it happen occasionally? Is the RMP bit cleared after every reception?

     

    There is failure of CAN interruption occasionally. According to the check of CANRMP, I found that it had been set to 1 and had not been reset to 0, so the interruption of gif failed and the interruption function failed. But I was really confused. In the interruption function, I judged the receive mailbox according to the bit of rmp and accepted the corresponding data, after that, I reset the corresponding rmp to 0. Theoretically there should be no RMP not reset to 0.

    Are you saying even though you clear RMP, there are still missed interrupts occasionally? Have you checked for the "Received Message Lost" condition? Is it possible you have a race condition? Meaning, the application is unable to service the interrupts promptly for the mailbox in question. If this could be the case, please open up a few more mailboxes with the same MSGID and use the OPC mechanism.

  • Hi Hareesh,

    This phenomenon will appear every time. If RMP is not cleared, the program will not enter the can receive interrupt. If adding a can before each can receive interrupt, then I can normally enter the can receive interrupt.
  • RMP bit must be cleared after every reception.

    This phenomenon will appear every time. If RMP is not cleared, the program will not enter the can receive interrupt. If adding a can before each can receive interrupt, then I can normally enter the can receive interrupt.

     In the above, I think you wanted to say "adding a clear before each can receive interrupt"

  • Hi Hareesh,

    I have been cleared RMP Bit. In fact, I am just can clear RMP bit 1 time when CAN received the data every 3 times.

    Thanks.

  • Sorry, I don’t understand what you mean by “I am just can clear RMP bit 1 time when CAN received the data every 3 times”. Please download SPRA876 and take a look at CAN_RXINT_A example. It shows how to implement Receive with interrupts.
  • Hi Hareesh ,

    I apologize for the inconvenience this issue caused. I have forwarded this answer to customer. Customer will continue to follow the post if his question has not been resolved.

    Thanks.